[ARM] S3C24XX: DMA: Split hardware regs out of <mach/dma.h>
The <mach/dma.h> is for the driver API for the DMA system and should not have anything relying on the CPU specific registers. Remove the registers to <plat/dma-regs.h> for the code that really needs to know about them. Signed-off-by: Ben Dooks <ben@simtec.co.uk> Signed-off-by: Ben Dooks <ben-linux@fluff.org>hifive-unleashed-5.1
Ben Dooks
Ben Dooks
parent
8970ef47d5
commit
44dc94045f
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@ -25,6 +25,7 @@
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#include <plat/regs-serial.h>
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#include <mach/regs-gpio.h>
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#include <plat/regs-ac97.h>
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#include <plat/regs-dma.h>
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#include <mach/regs-mem.h>
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#include <mach/regs-lcd.h>
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#include <mach/regs-sdi.h>
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@ -3,7 +3,7 @@
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* Copyright (C) 2003,2004,2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* Samsung S3C241XX DMA support
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* Samsung S3C24XX DMA support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -68,7 +68,6 @@ enum s3c2410_dma_state {
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S3C2410_DMA_PAUSED
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};
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/* enum s3c2410_dma_loadst
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*
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* This represents the state of the DMA engine, wrt to the loaded / running
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@ -311,138 +310,4 @@ extern int s3c2410_dma_getposition(unsigned int channel,
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extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
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extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
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/* DMA Register definitions */
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#define S3C2410_DMA_DISRC (0x00)
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#define S3C2410_DMA_DISRCC (0x04)
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#define S3C2410_DMA_DIDST (0x08)
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#define S3C2410_DMA_DIDSTC (0x0C)
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#define S3C2410_DMA_DCON (0x10)
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#define S3C2410_DMA_DSTAT (0x14)
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#define S3C2410_DMA_DCSRC (0x18)
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#define S3C2410_DMA_DCDST (0x1C)
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#define S3C2410_DMA_DMASKTRIG (0x20)
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#define S3C2412_DMA_DMAREQSEL (0x24)
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#define S3C2443_DMA_DMAREQSEL (0x24)
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#define S3C2410_DISRCC_INC (1<<0)
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#define S3C2410_DISRCC_APB (1<<1)
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#define S3C2410_DMASKTRIG_STOP (1<<2)
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#define S3C2410_DMASKTRIG_ON (1<<1)
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#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
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#define S3C2410_DCON_DEMAND (0<<31)
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#define S3C2410_DCON_HANDSHAKE (1<<31)
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#define S3C2410_DCON_SYNC_PCLK (0<<30)
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#define S3C2410_DCON_SYNC_HCLK (1<<30)
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#define S3C2410_DCON_INTREQ (1<<29)
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#define S3C2410_DCON_CH0_XDREQ0 (0<<24)
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#define S3C2410_DCON_CH0_UART0 (1<<24)
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#define S3C2410_DCON_CH0_SDI (2<<24)
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#define S3C2410_DCON_CH0_TIMER (3<<24)
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#define S3C2410_DCON_CH0_USBEP1 (4<<24)
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#define S3C2410_DCON_CH1_XDREQ1 (0<<24)
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#define S3C2410_DCON_CH1_UART1 (1<<24)
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#define S3C2410_DCON_CH1_I2SSDI (2<<24)
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#define S3C2410_DCON_CH1_SPI (3<<24)
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#define S3C2410_DCON_CH1_USBEP2 (4<<24)
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#define S3C2410_DCON_CH2_I2SSDO (0<<24)
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#define S3C2410_DCON_CH2_I2SSDI (1<<24)
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#define S3C2410_DCON_CH2_SDI (2<<24)
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#define S3C2410_DCON_CH2_TIMER (3<<24)
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#define S3C2410_DCON_CH2_USBEP3 (4<<24)
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#define S3C2410_DCON_CH3_UART2 (0<<24)
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#define S3C2410_DCON_CH3_SDI (1<<24)
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#define S3C2410_DCON_CH3_SPI (2<<24)
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#define S3C2410_DCON_CH3_TIMER (3<<24)
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#define S3C2410_DCON_CH3_USBEP4 (4<<24)
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#define S3C2410_DCON_SRCSHIFT (24)
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#define S3C2410_DCON_SRCMASK (7<<24)
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#define S3C2410_DCON_BYTE (0<<20)
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#define S3C2410_DCON_HALFWORD (1<<20)
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#define S3C2410_DCON_WORD (2<<20)
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#define S3C2410_DCON_AUTORELOAD (0<<22)
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#define S3C2410_DCON_NORELOAD (1<<22)
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#define S3C2410_DCON_HWTRIG (1<<23)
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#ifdef CONFIG_CPU_S3C2440
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#define S3C2440_DIDSTC_CHKINT (1<<2)
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#define S3C2440_DCON_CH0_I2SSDO (5<<24)
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#define S3C2440_DCON_CH0_PCMIN (6<<24)
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#define S3C2440_DCON_CH1_PCMOUT (5<<24)
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#define S3C2440_DCON_CH1_SDI (6<<24)
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#define S3C2440_DCON_CH2_PCMIN (5<<24)
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#define S3C2440_DCON_CH2_MICIN (6<<24)
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#define S3C2440_DCON_CH3_MICIN (5<<24)
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#define S3C2440_DCON_CH3_PCMOUT (6<<24)
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#endif
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#ifdef CONFIG_CPU_S3C2412
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#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1)
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#define S3C2412_DMAREQSEL_HW (1)
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#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
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#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
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#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
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#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
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#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
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#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
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#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
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#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
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#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
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#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
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#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
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#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
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#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
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#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
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#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
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#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
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#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
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#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
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#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
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#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
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#endif
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#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1)
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#define S3C2443_DMAREQSEL_HW (1)
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#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
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#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
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#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
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#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
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#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
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#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
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#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
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#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
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#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
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#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
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#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
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#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
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#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
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#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
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#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
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#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
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#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
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#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
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#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
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#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
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#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
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#endif /* __ASM_ARCH_DMA_H */
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@ -26,6 +26,7 @@
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#include <plat/regs-serial.h>
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#include <mach/regs-gpio.h>
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#include <plat/regs-ac97.h>
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#include <plat/regs-dma.h>
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#include <mach/regs-mem.h>
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#include <mach/regs-lcd.h>
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#include <mach/regs-sdi.h>
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@ -17,6 +17,7 @@
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#include <linux/sysdev.h>
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#include <linux/serial_core.h>
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#include <mach/map.h>
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#include <mach/dma.h>
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#include <plat/dma-plat.h>
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@ -25,6 +26,7 @@
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#include <plat/regs-serial.h>
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#include <mach/regs-gpio.h>
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#include <plat/regs-ac97.h>
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#include <plat/regs-dma.h>
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#include <mach/regs-mem.h>
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#include <mach/regs-lcd.h>
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#include <mach/regs-sdi.h>
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@ -26,6 +26,7 @@
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#include <plat/regs-serial.h>
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#include <mach/regs-gpio.h>
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#include <plat/regs-ac97.h>
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#include <plat/regs-dma.h>
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#include <mach/regs-mem.h>
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#include <mach/regs-lcd.h>
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#include <mach/regs-sdi.h>
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@ -31,10 +31,10 @@
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#include <asm/irq.h>
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#include <mach/hardware.h>
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#include <mach/dma.h>
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#include <mach/map.h>
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#include <plat/dma-plat.h>
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#include <plat/regs-dma.h>
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/* io map for dma */
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static void __iomem *dma_base;
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@ -0,0 +1,145 @@
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/* arch/arm/mach-s3c2410/include/mach/dma.h
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*
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* Copyright (C) 2003,2004,2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* Samsung S3C24XX DMA support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/* DMA Register definitions */
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#define S3C2410_DMA_DISRC (0x00)
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#define S3C2410_DMA_DISRCC (0x04)
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#define S3C2410_DMA_DIDST (0x08)
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#define S3C2410_DMA_DIDSTC (0x0C)
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#define S3C2410_DMA_DCON (0x10)
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#define S3C2410_DMA_DSTAT (0x14)
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#define S3C2410_DMA_DCSRC (0x18)
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#define S3C2410_DMA_DCDST (0x1C)
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#define S3C2410_DMA_DMASKTRIG (0x20)
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#define S3C2412_DMA_DMAREQSEL (0x24)
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#define S3C2443_DMA_DMAREQSEL (0x24)
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#define S3C2410_DISRCC_INC (1<<0)
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#define S3C2410_DISRCC_APB (1<<1)
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#define S3C2410_DMASKTRIG_STOP (1<<2)
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#define S3C2410_DMASKTRIG_ON (1<<1)
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#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
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#define S3C2410_DCON_DEMAND (0<<31)
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#define S3C2410_DCON_HANDSHAKE (1<<31)
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#define S3C2410_DCON_SYNC_PCLK (0<<30)
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#define S3C2410_DCON_SYNC_HCLK (1<<30)
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#define S3C2410_DCON_INTREQ (1<<29)
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#define S3C2410_DCON_CH0_XDREQ0 (0<<24)
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#define S3C2410_DCON_CH0_UART0 (1<<24)
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#define S3C2410_DCON_CH0_SDI (2<<24)
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#define S3C2410_DCON_CH0_TIMER (3<<24)
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#define S3C2410_DCON_CH0_USBEP1 (4<<24)
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#define S3C2410_DCON_CH1_XDREQ1 (0<<24)
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#define S3C2410_DCON_CH1_UART1 (1<<24)
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#define S3C2410_DCON_CH1_I2SSDI (2<<24)
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#define S3C2410_DCON_CH1_SPI (3<<24)
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#define S3C2410_DCON_CH1_USBEP2 (4<<24)
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#define S3C2410_DCON_CH2_I2SSDO (0<<24)
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#define S3C2410_DCON_CH2_I2SSDI (1<<24)
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#define S3C2410_DCON_CH2_SDI (2<<24)
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#define S3C2410_DCON_CH2_TIMER (3<<24)
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#define S3C2410_DCON_CH2_USBEP3 (4<<24)
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#define S3C2410_DCON_CH3_UART2 (0<<24)
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#define S3C2410_DCON_CH3_SDI (1<<24)
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#define S3C2410_DCON_CH3_SPI (2<<24)
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#define S3C2410_DCON_CH3_TIMER (3<<24)
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#define S3C2410_DCON_CH3_USBEP4 (4<<24)
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#define S3C2410_DCON_SRCSHIFT (24)
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#define S3C2410_DCON_SRCMASK (7<<24)
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#define S3C2410_DCON_BYTE (0<<20)
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#define S3C2410_DCON_HALFWORD (1<<20)
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#define S3C2410_DCON_WORD (2<<20)
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#define S3C2410_DCON_AUTORELOAD (0<<22)
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#define S3C2410_DCON_NORELOAD (1<<22)
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#define S3C2410_DCON_HWTRIG (1<<23)
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#ifdef CONFIG_CPU_S3C2440
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#define S3C2440_DIDSTC_CHKINT (1<<2)
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#define S3C2440_DCON_CH0_I2SSDO (5<<24)
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#define S3C2440_DCON_CH0_PCMIN (6<<24)
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#define S3C2440_DCON_CH1_PCMOUT (5<<24)
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#define S3C2440_DCON_CH1_SDI (6<<24)
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#define S3C2440_DCON_CH2_PCMIN (5<<24)
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#define S3C2440_DCON_CH2_MICIN (6<<24)
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#define S3C2440_DCON_CH3_MICIN (5<<24)
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#define S3C2440_DCON_CH3_PCMOUT (6<<24)
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#endif
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#ifdef CONFIG_CPU_S3C2412
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#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1)
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#define S3C2412_DMAREQSEL_HW (1)
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#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
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#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
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#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
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#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
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#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
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#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
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#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
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#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
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#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
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#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
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#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
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#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
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#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
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#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
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#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
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#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
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#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
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#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
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#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
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#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
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#endif
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#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1)
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#define S3C2443_DMAREQSEL_HW (1)
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#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
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#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
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#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
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#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
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#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
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#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
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#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
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#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
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#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
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#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
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#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
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#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
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#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
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#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
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#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
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#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
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#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
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#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
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#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
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#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
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#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
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Loading…
Reference in New Issue