Add ide-timing functionality to libata.
This is needed for full AMD and VIA drivers and possibly more. Functions to turn actual clocking and cycle timings into register values. Also to merge shared timings to compute an optimal timing set. Built from the drivers/ide version by Vojtech Pavlik Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>hifive-unleashed-5.1
Alan Cox
Jeff Garzik
parent
11e29e2151
commit
452503f993
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@ -1538,6 +1538,152 @@ void ata_port_disable(struct ata_port *ap)
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ap->flags |= ATA_FLAG_PORT_DISABLED;
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}
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/*
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* This mode timing computation functionality is ported over from
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* drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
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*/
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/*
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* PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
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* These were taken from ATA/ATAPI-6 standard, rev 0a, except
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* for PIO 5, which is a nonstandard extension and UDMA6, which
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* is currently supported only by Maxtor drives.
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*/
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static const struct ata_timing ata_timing[] = {
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{ XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
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{ XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
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{ XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
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{ XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
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{ XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
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{ XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
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{ XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
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/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 }, */
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{ XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
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{ XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
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{ XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
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{ XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
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{ XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
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{ XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
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/* { XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 }, */
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{ XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
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{ XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
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{ XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
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{ XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
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{ XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
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/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, */
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{ 0xFF }
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};
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#define ENOUGH(v,unit) (((v)-1)/(unit)+1)
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#define EZ(v,unit) ((v)?ENOUGH(v,unit):0)
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static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT)
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{
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q->setup = EZ(t->setup * 1000, T);
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q->act8b = EZ(t->act8b * 1000, T);
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q->rec8b = EZ(t->rec8b * 1000, T);
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q->cyc8b = EZ(t->cyc8b * 1000, T);
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q->active = EZ(t->active * 1000, T);
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q->recover = EZ(t->recover * 1000, T);
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q->cycle = EZ(t->cycle * 1000, T);
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q->udma = EZ(t->udma * 1000, UT);
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}
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void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
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struct ata_timing *m, unsigned int what)
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{
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if (what & ATA_TIMING_SETUP ) m->setup = max(a->setup, b->setup);
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if (what & ATA_TIMING_ACT8B ) m->act8b = max(a->act8b, b->act8b);
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if (what & ATA_TIMING_REC8B ) m->rec8b = max(a->rec8b, b->rec8b);
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if (what & ATA_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b);
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if (what & ATA_TIMING_ACTIVE ) m->active = max(a->active, b->active);
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if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover);
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if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle);
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if (what & ATA_TIMING_UDMA ) m->udma = max(a->udma, b->udma);
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}
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static const struct ata_timing* ata_timing_find_mode(unsigned short speed)
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{
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const struct ata_timing *t;
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for (t = ata_timing; t->mode != speed; t++)
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if (t->mode != 0xFF)
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return NULL;
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return t;
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}
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int ata_timing_compute(struct ata_device *adev, unsigned short speed,
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struct ata_timing *t, int T, int UT)
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{
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const struct ata_timing *s;
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struct ata_timing p;
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/*
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* Find the mode.
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*/
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if (!(s = ata_timing_find_mode(speed)))
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return -EINVAL;
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/*
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* If the drive is an EIDE drive, it can tell us it needs extended
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* PIO/MW_DMA cycle timing.
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*/
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if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
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memset(&p, 0, sizeof(p));
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if(speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) {
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if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO];
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else p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO_IORDY];
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} else if(speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) {
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p.cycle = adev->id[ATA_ID_EIDE_DMA_MIN];
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}
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ata_timing_merge(&p, t, t, ATA_TIMING_CYCLE | ATA_TIMING_CYC8B);
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}
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/*
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* Convert the timing to bus clock counts.
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*/
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ata_timing_quantize(s, t, T, UT);
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/*
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* Even in DMA/UDMA modes we still use PIO access for IDENTIFY, S.M.A.R.T
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* and some other commands. We have to ensure that the DMA cycle timing is
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* slower/equal than the fastest PIO timing.
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*/
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if (speed > XFER_PIO_4) {
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ata_timing_compute(adev, adev->pio_mode, &p, T, UT);
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ata_timing_merge(&p, t, t, ATA_TIMING_ALL);
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}
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/*
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* Lenghten active & recovery time so that cycle time is correct.
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*/
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if (t->act8b + t->rec8b < t->cyc8b) {
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t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
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t->rec8b = t->cyc8b - t->act8b;
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}
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if (t->active + t->recover < t->cycle) {
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t->active += (t->cycle - (t->active + t->recover)) / 2;
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t->recover = t->cycle - t->active;
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}
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return 0;
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}
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static struct {
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unsigned int shift;
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u8 base;
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@ -4764,6 +4910,9 @@ EXPORT_SYMBOL_GPL(ata_dev_id_string);
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EXPORT_SYMBOL_GPL(ata_dev_config);
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EXPORT_SYMBOL_GPL(ata_scsi_simulate);
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EXPORT_SYMBOL_GPL(ata_timing_compute);
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EXPORT_SYMBOL_GPL(ata_timing_merge);
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#ifdef CONFIG_PCI
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EXPORT_SYMBOL_GPL(pci_test_config_bits);
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EXPORT_SYMBOL_GPL(ata_pci_host_stop);
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@ -388,6 +388,19 @@ struct ata_port_info {
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struct ata_port_operations *port_ops;
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};
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struct ata_timing {
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unsigned short mode; /* ATA mode */
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unsigned short setup; /* t1 */
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unsigned short act8b; /* t2 for 8-bit I/O */
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unsigned short rec8b; /* t2i for 8-bit I/O */
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unsigned short cyc8b; /* t0 for 8-bit I/O */
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unsigned short active; /* t2 or tD */
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unsigned short recover; /* t2i or tK */
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unsigned short cycle; /* t0 */
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unsigned short udma; /* t2CYCTYP/2 */
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};
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#define FIT(v,vmin,vmax) max_t(short,min_t(short,v,vmax),vmin)
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extern void ata_port_probe(struct ata_port *);
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extern void __sata_phy_reset(struct ata_port *ap);
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@ -451,6 +464,32 @@ extern int ata_std_bios_param(struct scsi_device *sdev,
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sector_t capacity, int geom[]);
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extern int ata_scsi_slave_config(struct scsi_device *sdev);
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/*
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* Timing helpers
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*/
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extern int ata_timing_compute(struct ata_device *, unsigned short,
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struct ata_timing *, int, int);
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extern void ata_timing_merge(const struct ata_timing *,
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const struct ata_timing *, struct ata_timing *,
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unsigned int);
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enum {
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ATA_TIMING_SETUP = (1 << 0),
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ATA_TIMING_ACT8B = (1 << 1),
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ATA_TIMING_REC8B = (1 << 2),
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ATA_TIMING_CYC8B = (1 << 3),
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ATA_TIMING_8BIT = ATA_TIMING_ACT8B | ATA_TIMING_REC8B |
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ATA_TIMING_CYC8B,
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ATA_TIMING_ACTIVE = (1 << 4),
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ATA_TIMING_RECOVER = (1 << 5),
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ATA_TIMING_CYCLE = (1 << 6),
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ATA_TIMING_UDMA = (1 << 7),
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ATA_TIMING_ALL = ATA_TIMING_SETUP | ATA_TIMING_ACT8B |
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ATA_TIMING_REC8B | ATA_TIMING_CYC8B |
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ATA_TIMING_ACTIVE | ATA_TIMING_RECOVER |
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ATA_TIMING_CYCLE | ATA_TIMING_UDMA,
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};
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#ifdef CONFIG_PCI
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struct pci_bits {
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