drm/i915: panel power sequencing for VLV eDP v2
PPS register offsets have changed in Valleyview.
v2: don't clobber port select bits on VLV when fixing up PPS timings
don't bother with G4x PPS regs (Jani)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Jesse Barnes
Daniel Vetter
parent
b2634017b2
commit
453c542059
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@ -4112,6 +4112,15 @@
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#define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
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#define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
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#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
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#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
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#define VLV_PIPE_PP_ON_DELAYS(pipe) \
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_PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
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#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
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_PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
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#define VLV_PIPE_PP_DIVISOR(pipe) \
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_PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
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#define PCH_PP_STATUS 0xc7200
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#define PCH_PP_CONTROL 0xc7204
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#define PANEL_UNLOCK_REGS (0xabcd << 16)
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@ -274,16 +274,20 @@ static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
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{
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 pp_stat_reg;
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return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
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pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
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return (I915_READ(pp_stat_reg) & PP_ON) != 0;
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}
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static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
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{
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 pp_ctrl_reg;
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return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
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pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
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return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
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}
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static void
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@ -291,14 +295,19 @@ intel_dp_check_edp(struct intel_dp *intel_dp)
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{
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 pp_stat_reg, pp_ctrl_reg;
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if (!is_edp(intel_dp))
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return;
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pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
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pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
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if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
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WARN(1, "eDP powered off while attempting aux channel communication.\n");
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DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
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I915_READ(PCH_PP_STATUS),
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I915_READ(PCH_PP_CONTROL));
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I915_READ(pp_stat_reg),
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I915_READ(pp_ctrl_reg));
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}
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}
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@ -981,16 +990,20 @@ static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
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{
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 pp_stat_reg, pp_ctrl_reg;
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pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
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pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
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DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
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mask, value,
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I915_READ(PCH_PP_STATUS),
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I915_READ(PCH_PP_CONTROL));
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mask, value,
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I915_READ(pp_stat_reg),
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I915_READ(pp_ctrl_reg));
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if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
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if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
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DRM_ERROR("Panel status timeout: status %08x control %08x\n",
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I915_READ(PCH_PP_STATUS),
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I915_READ(PCH_PP_CONTROL));
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I915_READ(pp_stat_reg),
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I915_READ(pp_ctrl_reg));
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}
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}
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@ -1017,9 +1030,15 @@ static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
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* is locked
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*/
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static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
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static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
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{
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u32 control = I915_READ(PCH_PP_CONTROL);
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 control;
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u32 pp_ctrl_reg;
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pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
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control = I915_READ(pp_ctrl_reg);
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control &= ~PANEL_UNLOCK_MASK;
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control |= PANEL_UNLOCK_REGS;
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@ -1031,6 +1050,7 @@ void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 pp;
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u32 pp_stat_reg, pp_ctrl_reg;
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if (!is_edp(intel_dp))
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return;
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@ -1049,13 +1069,16 @@ void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
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if (!ironlake_edp_have_panel_power(intel_dp))
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ironlake_wait_panel_power_cycle(intel_dp);
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pp = ironlake_get_pp_control(dev_priv);
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pp = ironlake_get_pp_control(intel_dp);
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pp |= EDP_FORCE_VDD;
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I915_WRITE(PCH_PP_CONTROL, pp);
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POSTING_READ(PCH_PP_CONTROL);
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DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
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I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
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pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
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pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
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I915_WRITE(pp_ctrl_reg, pp);
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POSTING_READ(pp_ctrl_reg);
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DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
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I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
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/*
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* If the panel wasn't on, delay before accessing aux channel
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*/
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@ -1070,19 +1093,23 @@ static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 pp;
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u32 pp_stat_reg, pp_ctrl_reg;
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WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
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if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
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pp = ironlake_get_pp_control(dev_priv);
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pp = ironlake_get_pp_control(intel_dp);
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pp &= ~EDP_FORCE_VDD;
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I915_WRITE(PCH_PP_CONTROL, pp);
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POSTING_READ(PCH_PP_CONTROL);
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pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
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pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
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I915_WRITE(pp_ctrl_reg, pp);
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POSTING_READ(pp_ctrl_reg);
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/* Make sure sequencer is idle before allowing subsequent activity */
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DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
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I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
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DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
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I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
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msleep(intel_dp->panel_power_down_delay);
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}
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}
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@ -1126,6 +1153,7 @@ void ironlake_edp_panel_on(struct intel_dp *intel_dp)
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 pp;
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u32 pp_ctrl_reg;
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if (!is_edp(intel_dp))
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return;
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@ -1139,7 +1167,7 @@ void ironlake_edp_panel_on(struct intel_dp *intel_dp)
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ironlake_wait_panel_power_cycle(intel_dp);
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pp = ironlake_get_pp_control(dev_priv);
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pp = ironlake_get_pp_control(intel_dp);
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if (IS_GEN5(dev)) {
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/* ILK workaround: disable reset around power sequence */
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pp &= ~PANEL_POWER_RESET;
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@ -1151,8 +1179,10 @@ void ironlake_edp_panel_on(struct intel_dp *intel_dp)
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if (!IS_GEN5(dev))
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pp |= PANEL_POWER_RESET;
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I915_WRITE(PCH_PP_CONTROL, pp);
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POSTING_READ(PCH_PP_CONTROL);
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pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
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I915_WRITE(pp_ctrl_reg, pp);
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POSTING_READ(pp_ctrl_reg);
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ironlake_wait_panel_on(intel_dp);
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@ -1168,6 +1198,7 @@ void ironlake_edp_panel_off(struct intel_dp *intel_dp)
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 pp;
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u32 pp_ctrl_reg;
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if (!is_edp(intel_dp))
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return;
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@ -1176,12 +1207,15 @@ void ironlake_edp_panel_off(struct intel_dp *intel_dp)
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WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
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pp = ironlake_get_pp_control(dev_priv);
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pp = ironlake_get_pp_control(intel_dp);
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/* We need to switch off panel power _and_ force vdd, for otherwise some
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* panels get very unhappy and cease to work. */
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pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
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I915_WRITE(PCH_PP_CONTROL, pp);
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POSTING_READ(PCH_PP_CONTROL);
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pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
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I915_WRITE(pp_ctrl_reg, pp);
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POSTING_READ(pp_ctrl_reg);
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intel_dp->want_panel_vdd = false;
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@ -1195,6 +1229,7 @@ void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
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struct drm_i915_private *dev_priv = dev->dev_private;
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int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
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u32 pp;
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u32 pp_ctrl_reg;
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if (!is_edp(intel_dp))
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return;
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@ -1207,10 +1242,13 @@ void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
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* allowing it to appear.
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*/
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msleep(intel_dp->backlight_on_delay);
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pp = ironlake_get_pp_control(dev_priv);
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pp = ironlake_get_pp_control(intel_dp);
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pp |= EDP_BLC_ENABLE;
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I915_WRITE(PCH_PP_CONTROL, pp);
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POSTING_READ(PCH_PP_CONTROL);
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pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
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I915_WRITE(pp_ctrl_reg, pp);
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POSTING_READ(pp_ctrl_reg);
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intel_panel_enable_backlight(dev, pipe);
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}
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@ -1220,6 +1258,7 @@ void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 pp;
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u32 pp_ctrl_reg;
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if (!is_edp(intel_dp))
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return;
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@ -1227,10 +1266,13 @@ void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
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intel_panel_disable_backlight(dev);
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DRM_DEBUG_KMS("\n");
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pp = ironlake_get_pp_control(dev_priv);
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pp = ironlake_get_pp_control(intel_dp);
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pp &= ~EDP_BLC_ENABLE;
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I915_WRITE(PCH_PP_CONTROL, pp);
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POSTING_READ(PCH_PP_CONTROL);
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pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
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I915_WRITE(pp_ctrl_reg, pp);
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POSTING_READ(pp_ctrl_reg);
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msleep(intel_dp->backlight_off_delay);
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}
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@ -2620,15 +2662,28 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev,
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct edp_power_seq cur, vbt, spec, final;
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u32 pp_on, pp_off, pp_div, pp;
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int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
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if (HAS_PCH_SPLIT(dev)) {
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pp_control_reg = PCH_PP_CONTROL;
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pp_on_reg = PCH_PP_ON_DELAYS;
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pp_off_reg = PCH_PP_OFF_DELAYS;
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pp_div_reg = PCH_PP_DIVISOR;
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} else {
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pp_control_reg = PIPEA_PP_CONTROL;
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pp_on_reg = PIPEA_PP_ON_DELAYS;
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pp_off_reg = PIPEA_PP_OFF_DELAYS;
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pp_div_reg = PIPEA_PP_DIVISOR;
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}
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/* Workaround: Need to write PP_CONTROL with the unlock key as
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* the very first thing. */
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pp = ironlake_get_pp_control(dev_priv);
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I915_WRITE(PCH_PP_CONTROL, pp);
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pp = ironlake_get_pp_control(intel_dp);
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I915_WRITE(pp_control_reg, pp);
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pp_on = I915_READ(PCH_PP_ON_DELAYS);
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pp_off = I915_READ(PCH_PP_OFF_DELAYS);
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pp_div = I915_READ(PCH_PP_DIVISOR);
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pp_on = I915_READ(pp_on_reg);
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pp_off = I915_READ(pp_off_reg);
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pp_div = I915_READ(pp_div_reg);
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/* Pull timing values out of registers */
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cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
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@ -2703,7 +2758,22 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
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struct edp_power_seq *seq)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 pp_on, pp_off, pp_div;
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u32 pp_on, pp_off, pp_div, port_sel = 0;
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int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
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int pp_on_reg, pp_off_reg, pp_div_reg;
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if (HAS_PCH_SPLIT(dev)) {
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pp_on_reg = PCH_PP_ON_DELAYS;
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pp_off_reg = PCH_PP_OFF_DELAYS;
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pp_div_reg = PCH_PP_DIVISOR;
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} else {
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pp_on_reg = PIPEA_PP_ON_DELAYS;
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pp_off_reg = PIPEA_PP_OFF_DELAYS;
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pp_div_reg = PIPEA_PP_DIVISOR;
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}
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if (IS_VALLEYVIEW(dev))
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port_sel = I915_READ(pp_on_reg) & 0xc0000000;
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/* And finally store the new values in the power sequencer. */
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pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
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@ -2712,8 +2782,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
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(seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
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/* Compute the divisor for the pp clock, simply match the Bspec
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* formula. */
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pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
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<< PP_REFERENCE_DIVIDER_SHIFT;
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pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
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pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
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<< PANEL_POWER_CYCLE_DELAY_SHIFT);
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@ -2721,19 +2790,21 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
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* power sequencer any more. */
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if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
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if (is_cpu_edp(intel_dp))
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pp_on |= PANEL_POWER_PORT_DP_A;
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port_sel = PANEL_POWER_PORT_DP_A;
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else
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pp_on |= PANEL_POWER_PORT_DP_D;
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port_sel = PANEL_POWER_PORT_DP_D;
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}
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I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
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I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
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I915_WRITE(PCH_PP_DIVISOR, pp_div);
|
||||
pp_on |= port_sel;
|
||||
|
||||
I915_WRITE(pp_on_reg, pp_on);
|
||||
I915_WRITE(pp_off_reg, pp_off);
|
||||
I915_WRITE(pp_div_reg, pp_div);
|
||||
|
||||
DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
|
||||
I915_READ(PCH_PP_ON_DELAYS),
|
||||
I915_READ(PCH_PP_OFF_DELAYS),
|
||||
I915_READ(PCH_PP_DIVISOR));
|
||||
I915_READ(pp_on_reg),
|
||||
I915_READ(pp_off_reg),
|
||||
I915_READ(pp_div_reg));
|
||||
}
|
||||
|
||||
void
|
||||
|
|
|
|||
Loading…
Reference in a new issue