drm/amdgpu: fix the build on big endian
Some leftover copy and pastes from radeon that never got updated. Reviewed-by: Christian König <christian.koenig@amd.com> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -411,7 +411,8 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
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rb_bufsz = order_base_2(ring->ring_size / 4);
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rb_cntl = rb_bufsz << 1;
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#ifdef __BIG_ENDIAN
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rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE;
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rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
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SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
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#endif
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WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
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@ -2881,7 +2881,7 @@ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
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rb_bufsz = order_base_2(ring->ring_size / 8);
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tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
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#ifdef __BIG_ENDIAN
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tmp |= BUF_SWAP_32BIT;
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tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
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#endif
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WREG32(mmCP_RB0_CNTL, tmp);
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@ -3400,7 +3400,8 @@ static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
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mqd->queue_state.cp_hqd_pq_control |=
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(order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
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#ifdef __BIG_ENDIAN
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mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT;
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mqd->queue_state.cp_hqd_pq_control |=
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2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
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#endif
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mqd->queue_state.cp_hqd_pq_control &=
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~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
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