soc/tegra: pmc: Configure core power request polarity
This patch configures polarity of the core power request signal in PMC control register based on the device tree property. PMC asserts and de-asserts power request signal based on it polarity when it need to power-up and power-down the core rail during SC7. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -56,6 +56,7 @@
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#define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
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#define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
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#define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
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#define PMC_CNTRL_PWRREQ_POLARITY BIT(8)
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#define PMC_CNTRL_MAIN_RST BIT(4)
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#define PMC_WAKE_MASK 0x0c
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@ -2316,6 +2317,11 @@ static void tegra20_pmc_init(struct tegra_pmc *pmc)
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else
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value |= PMC_CNTRL_SYSCLK_POLARITY;
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if (pmc->corereq_high)
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value &= ~PMC_CNTRL_PWRREQ_POLARITY;
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else
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value |= PMC_CNTRL_PWRREQ_POLARITY;
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/* configure the output polarity while the request is tristated */
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tegra_pmc_writel(pmc, value, PMC_CNTRL);
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