soc: mediatek: pwrap: add support for MT8516 pwrap
Add the code to support the pwrap IP on the MediaTek MT8516 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>hifive-unleashed-5.2
Fabien Parent
Matthias Brugger
parent
a51f4c031d
commit
45a0686b91
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@ -381,6 +381,10 @@ enum pwrap_regs {
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PWRAP_EXT_GPS_AUXADC_RDATA_ADDR,
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PWRAP_GPSINF_0_STA,
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PWRAP_GPSINF_1_STA,
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/* MT8516 only regs */
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PWRAP_OP_TYPE,
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PWRAP_MSB_FIRST,
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};
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static int mt2701_regs[] = {
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@ -852,6 +856,91 @@ static int mt8183_regs[] = {
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[PWRAP_WACS2_VLDCLR] = 0xC28,
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};
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static int mt8516_regs[] = {
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[PWRAP_MUX_SEL] = 0x0,
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[PWRAP_WRAP_EN] = 0x4,
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[PWRAP_DIO_EN] = 0x8,
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[PWRAP_SIDLY] = 0xc,
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[PWRAP_RDDMY] = 0x10,
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[PWRAP_SI_CK_CON] = 0x14,
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[PWRAP_CSHEXT_WRITE] = 0x18,
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[PWRAP_CSHEXT_READ] = 0x1c,
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[PWRAP_CSLEXT_START] = 0x20,
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[PWRAP_CSLEXT_END] = 0x24,
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[PWRAP_STAUPD_PRD] = 0x28,
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[PWRAP_STAUPD_GRPEN] = 0x2c,
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[PWRAP_STAUPD_MAN_TRIG] = 0x40,
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[PWRAP_STAUPD_STA] = 0x44,
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[PWRAP_WRAP_STA] = 0x48,
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[PWRAP_HARB_INIT] = 0x4c,
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[PWRAP_HARB_HPRIO] = 0x50,
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[PWRAP_HIPRIO_ARB_EN] = 0x54,
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[PWRAP_HARB_STA0] = 0x58,
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[PWRAP_HARB_STA1] = 0x5c,
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[PWRAP_MAN_EN] = 0x60,
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[PWRAP_MAN_CMD] = 0x64,
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[PWRAP_MAN_RDATA] = 0x68,
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[PWRAP_MAN_VLDCLR] = 0x6c,
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[PWRAP_WACS0_EN] = 0x70,
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[PWRAP_INIT_DONE0] = 0x74,
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[PWRAP_WACS0_CMD] = 0x78,
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[PWRAP_WACS0_RDATA] = 0x7c,
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[PWRAP_WACS0_VLDCLR] = 0x80,
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[PWRAP_WACS1_EN] = 0x84,
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[PWRAP_INIT_DONE1] = 0x88,
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[PWRAP_WACS1_CMD] = 0x8c,
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[PWRAP_WACS1_RDATA] = 0x90,
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[PWRAP_WACS1_VLDCLR] = 0x94,
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[PWRAP_WACS2_EN] = 0x98,
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[PWRAP_INIT_DONE2] = 0x9c,
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[PWRAP_WACS2_CMD] = 0xa0,
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[PWRAP_WACS2_RDATA] = 0xa4,
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[PWRAP_WACS2_VLDCLR] = 0xa8,
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[PWRAP_INT_EN] = 0xac,
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[PWRAP_INT_FLG_RAW] = 0xb0,
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[PWRAP_INT_FLG] = 0xb4,
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[PWRAP_INT_CLR] = 0xb8,
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[PWRAP_SIG_ADR] = 0xbc,
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[PWRAP_SIG_MODE] = 0xc0,
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[PWRAP_SIG_VALUE] = 0xc4,
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[PWRAP_SIG_ERRVAL] = 0xc8,
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[PWRAP_CRC_EN] = 0xcc,
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[PWRAP_TIMER_EN] = 0xd0,
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[PWRAP_TIMER_STA] = 0xd4,
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[PWRAP_WDT_UNIT] = 0xd8,
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[PWRAP_WDT_SRC_EN] = 0xdc,
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[PWRAP_WDT_FLG] = 0xe0,
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[PWRAP_DEBUG_INT_SEL] = 0xe4,
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[PWRAP_DVFS_ADR0] = 0xe8,
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[PWRAP_DVFS_WDATA0] = 0xec,
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[PWRAP_DVFS_ADR1] = 0xf0,
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[PWRAP_DVFS_WDATA1] = 0xf4,
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[PWRAP_DVFS_ADR2] = 0xf8,
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[PWRAP_DVFS_WDATA2] = 0xfc,
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[PWRAP_DVFS_ADR3] = 0x100,
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[PWRAP_DVFS_WDATA3] = 0x104,
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[PWRAP_DVFS_ADR4] = 0x108,
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[PWRAP_DVFS_WDATA4] = 0x10c,
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[PWRAP_DVFS_ADR5] = 0x110,
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[PWRAP_DVFS_WDATA5] = 0x114,
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[PWRAP_DVFS_ADR6] = 0x118,
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[PWRAP_DVFS_WDATA6] = 0x11c,
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[PWRAP_DVFS_ADR7] = 0x120,
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[PWRAP_DVFS_WDATA7] = 0x124,
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[PWRAP_SPMINF_STA] = 0x128,
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[PWRAP_CIPHER_KEY_SEL] = 0x12c,
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[PWRAP_CIPHER_IV_SEL] = 0x130,
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[PWRAP_CIPHER_EN] = 0x134,
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[PWRAP_CIPHER_RDY] = 0x138,
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[PWRAP_CIPHER_MODE] = 0x13c,
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[PWRAP_CIPHER_SWRST] = 0x140,
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[PWRAP_DCM_EN] = 0x144,
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[PWRAP_DCM_DBC_PRD] = 0x148,
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[PWRAP_SW_RST] = 0x168,
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[PWRAP_OP_TYPE] = 0x16c,
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[PWRAP_MSB_FIRST] = 0x170,
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};
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enum pmic_type {
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PMIC_MT6323,
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PMIC_MT6351,
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@ -869,6 +958,7 @@ enum pwrap_type {
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PWRAP_MT8135,
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PWRAP_MT8173,
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PWRAP_MT8183,
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PWRAP_MT8516,
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};
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struct pmic_wrapper;
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@ -1297,6 +1387,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
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case PWRAP_MT6765:
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case PWRAP_MT6797:
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case PWRAP_MT8173:
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case PWRAP_MT8516:
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pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
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break;
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case PWRAP_MT7622:
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@ -1765,6 +1856,18 @@ static const struct pmic_wrapper_type pwrap_mt8183 = {
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.init_soc_specific = pwrap_mt8183_init_soc_specific,
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};
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static struct pmic_wrapper_type pwrap_mt8516 = {
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.regs = mt8516_regs,
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.type = PWRAP_MT8516,
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.arb_en_all = 0xff,
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.int_en_all = ~(u32)(BIT(31) | BIT(2)),
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.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
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.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
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.caps = PWRAP_CAP_DCM,
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.init_reg_clock = pwrap_mt2701_init_reg_clock,
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.init_soc_specific = NULL,
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};
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static const struct of_device_id of_pwrap_match_tbl[] = {
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{
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.compatible = "mediatek,mt2701-pwrap",
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@ -1787,6 +1890,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = {
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}, {
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.compatible = "mediatek,mt8183-pwrap",
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.data = &pwrap_mt8183,
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}, {
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.compatible = "mediatek,mt8516-pwrap",
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.data = &pwrap_mt8516,
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}, {
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/* sentinel */
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}
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