PCI: change PCI nomenclature in drivers/pci/ (comment changes)
Changing occurrences of variants of PCI-X and PCIe to the PCI-SIG terms listed in the "Trademark and Logo Usage Guidelines". http://www.pcisig.com/developers/procedures/logos/Trademark_and_Logo_Usage_Guidelines_updated_112206.pdf Patch is limited to drivers/pci/ and changes concern comments only. Signed-off-by: Stefan Assmann <sassmann@redhat.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>hifive-unleashed-5.1
Stefan Assmann
Jesse Barnes
parent
5714868812
commit
45e829ea41
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@ -121,7 +121,7 @@ struct controller {
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#define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450
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#define PCI_DEVICE_ID_AMD_POGO_7458 0x7458
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/* AMD PCIX bridge registers */
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/* AMD PCI-X bridge registers */
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#define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C
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#define PCIX_MISCII_OFFSET 0x48
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#define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80
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@ -304,7 +304,7 @@ struct device_domain_info {
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int segment; /* PCI domain */
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u8 bus; /* PCI bus number */
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u8 devfn; /* PCI devfn number */
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struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
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struct pci_dev *dev; /* it's NULL for PCIe-to-PCI bridge */
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struct intel_iommu *iommu; /* IOMMU used by this device */
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struct dmar_domain *domain; /* pointer to domain */
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};
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@ -1611,7 +1611,7 @@ domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
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return ret;
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parent = parent->bus->self;
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}
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if (pci_is_pcie(tmp)) /* this is a PCIE-to-PCI bridge */
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if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
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return domain_context_mapping_one(domain,
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pci_domain_nr(tmp->subordinate),
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tmp->subordinate->number, 0,
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@ -3319,7 +3319,7 @@ static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
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parent->devfn);
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parent = parent->bus->self;
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}
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if (pci_is_pcie(tmp)) /* this is a PCIE-to-PCI bridge */
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if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
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iommu_detach_dev(iommu,
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tmp->subordinate->number, 0);
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else /* this is a legacy PCI bridge */
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@ -528,7 +528,7 @@ int set_msi_sid(struct irte *irte, struct pci_dev *dev)
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bridge = pci_find_upstream_pcie_bridge(dev);
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if (bridge) {
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if (pci_is_pcie(bridge))/* this is a PCIE-to-PCI/PCIX bridge */
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if (pci_is_pcie(bridge))/* this is a PCIe-to-PCI/PCIX bridge */
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set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
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(bridge->bus->number << 8) | dev->bus->number);
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else /* this is a legacy PCI bridge */
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@ -1153,11 +1153,11 @@ pci_disable_device(struct pci_dev *dev)
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/**
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* pcibios_set_pcie_reset_state - set reset state for device dev
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* @dev: the PCI-E device reset
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* @dev: the PCIe device reset
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* @state: Reset state to enter into
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*
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*
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* Sets the PCI-E reset state for the device. This is the default
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* Sets the PCIe reset state for the device. This is the default
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* implementation. Architecture implementations can override this.
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*/
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int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
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@ -1168,7 +1168,7 @@ int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
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/**
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* pci_set_pcie_reset_state - set reset state for device dev
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* @dev: the PCI-E device reset
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* @dev: the PCIe device reset
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* @state: Reset state to enter into
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*
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*
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@ -1,7 +1,7 @@
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/*
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* PCIE AER software error injection support.
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* PCIe AER software error injection support.
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*
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* Debuging PCIE AER code is quite difficult because it is hard to
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* Debuging PCIe AER code is quite difficult because it is hard to
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* trigger various real hardware errors. Software based error
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* injection can fake almost all kinds of errors with the help of a
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* user space helper tool aer-inject, which can be gotten from:
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@ -155,7 +155,7 @@ static struct aer_rpc *aer_alloc_rpc(struct pcie_device *dev)
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mutex_init(&rpc->rpc_mutex);
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init_waitqueue_head(&rpc->wait_release);
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/* Use PCIE bus function to store rpc into PCIE device */
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/* Use PCIe bus function to store rpc into PCIe device */
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set_service_data(dev, rpc);
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return rpc;
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@ -24,7 +24,7 @@
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*
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* @return: Zero on success. Nonzero otherwise.
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*
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* Invoked when PCIE bus loads AER service driver. To avoid conflict with
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* Invoked when PCIe bus loads AER service driver. To avoid conflict with
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* BIOS AER support requires BIOS to yield AER control to OS native driver.
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**/
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int aer_osc_setup(struct pcie_device *pciedev)
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@ -587,7 +587,7 @@ static void handle_error_source(struct pcie_device *aerdev,
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* aer_enable_rootport - enable Root Port's interrupts when receiving messages
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* @rpc: pointer to a Root Port data structure
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*
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* Invoked when PCIE bus loads AER service driver.
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* Invoked when PCIe bus loads AER service driver.
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*/
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void aer_enable_rootport(struct aer_rpc *rpc)
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{
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@ -597,7 +597,7 @@ void aer_enable_rootport(struct aer_rpc *rpc)
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u32 reg32;
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pos = pci_pcie_cap(pdev);
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/* Clear PCIE Capability's Device Status */
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/* Clear PCIe Capability's Device Status */
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pci_read_config_word(pdev, pos+PCI_EXP_DEVSTA, ®16);
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pci_write_config_word(pdev, pos+PCI_EXP_DEVSTA, reg16);
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@ -631,7 +631,7 @@ void aer_enable_rootport(struct aer_rpc *rpc)
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* disable_root_aer - disable Root Port's interrupts when receiving messages
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* @rpc: pointer to a Root Port data structure
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*
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* Invoked when PCIE bus unloads AER service driver.
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* Invoked when PCIe bus unloads AER service driver.
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*/
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static void disable_root_aer(struct aer_rpc *rpc)
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{
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@ -1,6 +1,6 @@
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/*
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* File: drivers/pci/pcie/aspm.c
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* Enabling PCIE link L0s/L1 state and Clock Power Management
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* Enabling PCIe link L0s/L1 state and Clock Power Management
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*
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* Copyright (C) 2007 Intel
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* Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
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@ -499,7 +499,7 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
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int pos;
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u32 reg32;
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/*
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* Some functions in a slot might not all be PCIE functions,
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* Some functions in a slot might not all be PCIe functions,
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* very strange. Disable ASPM for the whole slot
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*/
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list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
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@ -15,9 +15,9 @@
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DECLARE_RWSEM(pci_bus_sem);
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/*
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* find the upstream PCIE-to-PCI bridge of a PCI device
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* find the upstream PCIe-to-PCI bridge of a PCI device
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* if the device is PCIE, return NULL
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* if the device isn't connected to a PCIE bridge (that is its parent is a
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* if the device isn't connected to a PCIe bridge (that is its parent is a
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* legacy PCI bridge and the bridge is directly connected to bus 0), return its
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* parent
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*/
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@ -37,7 +37,7 @@ pci_find_upstream_pcie_bridge(struct pci_dev *pdev)
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tmp = pdev;
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continue;
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}
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/* PCI device should connect to a PCIE bridge */
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/* PCI device should connect to a PCIe bridge */
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if (pdev->pcie_type != PCI_EXP_TYPE_PCI_BRIDGE) {
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/* Busted hardware? */
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WARN_ON_ONCE(1);
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