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[ARM] 4311/1: ixp4xx: add KIXRP435 platform 

Add Intel KIXRP435 Reference Platform based on IXP43x processor.
Fixed after review : access to cp15 removed in identification functions,
used access to global processor_id instead

Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com>
Signed-off-by: Ruslan  Sushko <rsushko@ru.mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
hifive-unleashed-5.1
Ruslan V. Sushko 2007-04-06 15:00:31 +01:00 committed by Russell King
parent 25735d10ba
commit 45fba0846f
12 changed files with 106 additions and 19 deletions
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2
arch/arm/configs/ixp4xx_defconfig
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@ -117,11 +117,13 @@ CONFIG_ARCH_ADI_COYOTE=y
CONFIG_ARCH_IXDP425=y
CONFIG_MACH_IXDPG425=y
CONFIG_MACH_IXDP465=y
CONFIG_MACH_KIXRP435=y
CONFIG_ARCH_IXCDP1100=y
CONFIG_ARCH_PRPMC1100=y
CONFIG_MACH_NAS100D=y
CONFIG_ARCH_IXDP4XX=y
CONFIG_CPU_IXP46X=y
CONFIG_CPU_IXP43X=y
# CONFIG_MACH_GTWX5715 is not set
#

13
arch/arm/mach-ixp4xx/Kconfig
View File

@ -62,6 +62,12 @@ config MACH_IXDP465
IXDP465 Development Platform (Also known as BMP).
For more information on this platform, see <file:Documentation/arm/IXP4xx>.
config MACH_KIXRP435
bool "KIXRP435"
help
Say 'Y' here if you want your kernel to support Intel's
KIXRP435 Reference Platform.
For more information on this platform, see <file:Documentation/arm/IXP4xx>.
#
# IXCDP1100 is the exact same HW as IXDP425, but with a different machine
@ -94,7 +100,7 @@ config MACH_NAS100D
#
config ARCH_IXDP4XX
bool
depends on ARCH_IXDP425 || MACH_IXDP465
depends on ARCH_IXDP425 || MACH_IXDP465 || MACH_KIXRP435
default y
#
@ -105,6 +111,11 @@ config CPU_IXP46X
depends on MACH_IXDP465
default y
config CPU_IXP43X
bool
depends on MACH_KIXRP435
default y
config MACH_GTWX5715
bool "Gemtek WX5715 (Linksys WRV54G)"
depends on ARCH_IXP4XX

4
arch/arm/mach-ixp4xx/common-pci.c
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@ -374,7 +374,7 @@ void __init ixp4xx_pci_preinit(void)
* Determine which PCI read method to use.
* Rev 0 IXP425 requires workaround.
*/
if (!(processor_id & 0xf) && !cpu_is_ixp46x()) {
if (!(processor_id & 0xf) && cpu_is_ixp42x()) {
printk("PCI: IXP42x A0 silicon detected - "
"PCI Non-Prefetch Workaround Enabled\n");
ixp4xx_pci_read = ixp4xx_pci_read_errata;
@ -480,7 +480,7 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
res[0].flags = IORESOURCE_IO;
res[1].name = "PCI Memory Space";
res[1].start = 0x48000000;
res[1].start = PCIBIOS_MIN_MEM;
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
res[1].end = 0x4bffffff;
#else

6
arch/arm/mach-ixp4xx/common.c
View File

@ -192,7 +192,7 @@ static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
static void ixp4xx_irq_mask(unsigned int irq)
{
if (cpu_is_ixp46x() && irq >= 32)
if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32)
*IXP4XX_ICMR2 &= ~(1 << (irq - 32));
else
*IXP4XX_ICMR &= ~(1 << irq);
@ -215,7 +215,7 @@ static void ixp4xx_irq_unmask(unsigned int irq)
if (!(ixp4xx_irq_edge & (1 << irq)))
ixp4xx_irq_ack(irq);
if (cpu_is_ixp46x() && irq >= 32)
if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32)
*IXP4XX_ICMR2 |= (1 << (irq - 32));
else
*IXP4XX_ICMR |= (1 << irq);
@ -239,7 +239,7 @@ void __init ixp4xx_init_irq(void)
/* Disable all interrupt */
*IXP4XX_ICMR = 0x0;
if (cpu_is_ixp46x()) {
if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
/* Route upper 32 sources to IRQ instead of FIQ */
*IXP4XX_ICLR2 = 0x00;

2
arch/arm/mach-ixp4xx/ixdp425-pci.c
View File

@ -66,7 +66,7 @@ struct hw_pci ixdp425_pci __initdata = {
int __init ixdp425_pci_init(void)
{
if (machine_is_ixdp425() || machine_is_ixcdp1100() ||
machine_is_ixdp465())
machine_is_ixdp465() || machine_is_kixrp435())
pci_common_init(&ixdp425_pci);
return 0;
}

18
arch/arm/mach-ixp4xx/ixdp425-setup.c
View File

@ -115,6 +115,11 @@ static void __init ixdp425_init(void)
ixdp425_flash_resource.end =
IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
if (cpu_is_ixp43x()) {
ixdp425_uart.num_resources = 1;
ixdp425_uart_data[1].flags = 0;
}
platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices));
}
@ -156,3 +161,16 @@ MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
.init_machine = ixdp425_init,
MACHINE_END
#endif
#ifdef CONFIG_MACH_KIXRP435
MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
/* Maintainer: MontaVista Software, Inc. */
.phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
.io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
.map_io = ixp4xx_map_io,
.init_irq = ixp4xx_init_irq,
.timer = &ixp4xx_timer,
.boot_params = 0x0100,
.init_machine = ixdp425_init,
MACHINE_END
#endif

28
arch/arm/mm/proc-xscale.S
View File

@ -584,6 +584,11 @@ cpu_ixp42x_name:
.asciz "XScale-IXP42x Family"
.size cpu_ixp42x_name, . - cpu_ixp42x_name
.type cpu_ixp43x_name, #object
cpu_ixp43x_name:
.asciz "XScale-IXP43x Family"
.size cpu_ixp43x_name, . - cpu_ixp43x_name
.type cpu_ixp46x_name, #object
cpu_ixp46x_name:
.asciz "XScale-IXP46x Family"
@ -843,6 +848,29 @@ __ixp42x_proc_info:
.long xscale_cache_fns
.size __ixp42x_proc_info, . - __ixp42x_proc_info
.type __ixp43x_proc_info, #object
__ixp43x_proc_info:
.long 0x69054040
.long 0xfffffff0
.long PMD_TYPE_SECT | \
PMD_SECT_BUFFERABLE | \
PMD_SECT_CACHEABLE | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
.long PMD_TYPE_SECT | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
b __xscale_setup
.long cpu_arch_name
.long cpu_elf_name
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
.long cpu_ixp43x_name
.long xscale_processor_functions
.long v4wbi_tlb_fns
.long xscale_mc_user_fns
.long xscale_cache_fns
.size __ixp43x_proc_info, . - __ixp43x_proc_info
.type __ixp46x_proc_info, #object
__ixp46x_proc_info:
.long 0x69054200

4
include/asm-arm/arch-ixp4xx/entry-macro.S
View File

@ -31,9 +31,9 @@
1001:
/*
* IXP465 has an upper IRQ status register
* IXP465/IXP435 has an upper IRQ status register
*/
#if defined(CONFIG_CPU_IXP46X)
#if defined(CONFIG_CPU_IXP46X) || defined(CONFIG_CPU_IXP43X)
ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET)
ldr \irqstat, [\irqstat] @ get upper interrupts
mov \irqnr, #63

4
include/asm-arm/arch-ixp4xx/hardware.h
View File

@ -17,8 +17,8 @@
#ifndef __ASM_ARCH_HARDWARE_H__
#define __ASM_ARCH_HARDWARE_H__
#define PCIBIOS_MIN_IO 0x00001000
#define PCIBIOS_MIN_MEM 0x48000000
#define PCIBIOS_MIN_IO 0x00001000
#define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x40000000 : 0x48000000)
/*
* We override the standard dma-mask routines for bouncing.

2
include/asm-arm/arch-ixp4xx/io.h
View File

@ -61,7 +61,7 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
static inline void __iomem *
__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned long flags)
{
if((addr < 0x48000000) || (addr > 0x4fffffff))
if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff))
return __ioremap(addr, size, flags);
return (void *)addr;

6
include/asm-arm/arch-ixp4xx/irqs.h
View File

@ -62,10 +62,10 @@
/*
* Only first 32 sources are valid if running on IXP42x systems
*/
#ifndef CONFIG_CPU_IXP46X
#define NR_IRQS 32
#else
#if defined(CONFIG_CPU_IXP46X) || defined(CONFIG_CPU_IXP43X)
#define NR_IRQS 64
#else
#define NR_IRQS 32
#endif
#define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU)

36
include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
View File

@ -607,15 +607,43 @@
#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
/* Processor id value in CP15 Register 0 */
#define IXP425_PROCESSOR_ID_VALUE 0x690541c0
#define IXP435_PROCESSOR_ID_VALUE 0x69054040
#define IXP465_PROCESSOR_ID_VALUE 0x69054200
#define IXP4XX_PROCESSOR_ID_MASK 0xfffffff0
#ifndef __ASSEMBLY__
static inline int cpu_is_ixp42x(void)
{
extern unsigned int processor_id;
if ((processor_id & IXP4XX_PROCESSOR_ID_MASK) ==
IXP425_PROCESSOR_ID_VALUE )
return 1;
return 0;
}
static inline int cpu_is_ixp43x(void)
{
#ifdef CONFIG_CPU_IXP43X
extern unsigned int processor_id;
if ((processor_id & IXP4XX_PROCESSOR_ID_MASK) ==
IXP435_PROCESSOR_ID_VALUE )
return 1;
#endif
return 0;
}
static inline int cpu_is_ixp46x(void)
{
#ifdef CONFIG_CPU_IXP46X
unsigned int processor_id;
extern unsigned int processor_id;
asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :);
if ((processor_id & 0xffffff00) == 0x69054200)
if ((processor_id & IXP4XX_PROCESSOR_ID_MASK) ==
IXP465_PROCESSOR_ID_VALUE )
return 1;
#endif
return 0;