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x86/vector: Switch IOAPIC to global reservation mode 

IOAPICs install and allocate vectors for inactive interrupts. This results
in problems on CPU offline and wastes vector resources for nothing.

Handle inactive IOAPIC interrupts in the same way as inactive MSI
interrupts and switch them to the global reservation mode.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Juergen Gross <jgross@suse.com>
Tested-by: Yu Chen <yu.c.chen@intel.com>
Acked-by: Juergen Gross <jgross@suse.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Alok Kataria <akataria@vmware.com>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Rui Zhang <rui.zhang@intel.com>
Cc: "K. Y. Srinivasan" <kys@microsoft.com>
Cc: Arjan van de Ven <arjan@linux.intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Len Brown <lenb@kernel.org>
Link: https://lkml.kernel.org/r/20170913213156.273454591@linutronix.de
hifive-unleashed-5.1
Thomas Gleixner 2017-09-13 23:29:52 +02:00
parent 4900be8360
commit 464d12309e
1 changed files with 33 additions and 23 deletions
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56
arch/x86/kernel/apic/vector.c
View File

@ -258,17 +258,6 @@ static int assign_irq_vector_any_locked(struct irq_data *irqd)
return assign_vector_locked(irqd, cpu_online_mask);
}
static int assign_irq_vector_any(struct irq_data *irqd)
{
unsigned long flags;
int ret;
raw_spin_lock_irqsave(&vector_lock, flags);
ret = assign_irq_vector_any_locked(irqd);
raw_spin_unlock_irqrestore(&vector_lock, flags);
return ret;
}
static int
assign_irq_vector_policy(struct irq_data *irqd, struct irq_alloc_info *info)
{
@ -276,10 +265,10 @@ assign_irq_vector_policy(struct irq_data *irqd, struct irq_alloc_info *info)
return reserve_managed_vector(irqd);
if (info->mask)
return assign_irq_vector(irqd, info->mask);
if (info->type != X86_IRQ_ALLOC_TYPE_MSI &&
info->type != X86_IRQ_ALLOC_TYPE_MSIX)
return assign_irq_vector_any(irqd);
/* For MSI(X) make only a global reservation with no guarantee */
/*
* Make only a global reservation with no guarantee. A real vector
* is associated at activation time.
*/
return reserve_irq_vector(irqd);
}
@ -456,13 +445,39 @@ static void x86_vector_free_irqs(struct irq_domain *domain,
}
}
static bool vector_configure_legacy(unsigned int virq, struct irq_data *irqd,
struct apic_chip_data *apicd)
{
unsigned long flags;
bool realloc = false;
apicd->vector = ISA_IRQ_VECTOR(virq);
apicd->cpu = 0;
raw_spin_lock_irqsave(&vector_lock, flags);
/*
* If the interrupt is activated, then it must stay at this vector
* position. That's usually the timer interrupt (0).
*/
if (irqd_is_activated(irqd)) {
trace_vector_setup(virq, true, 0);
apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu);
} else {
/* Release the vector */
apicd->can_reserve = true;
clear_irq_vector(irqd);
realloc = true;
}
raw_spin_unlock_irqrestore(&vector_lock, flags);
return realloc;
}
static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *arg)
{
struct irq_alloc_info *info = arg;
struct apic_chip_data *apicd;
struct irq_data *irqd;
unsigned long flags;
int i, err, node;
if (disable_apic)
@ -496,13 +511,8 @@ static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
* config.
*/
if (info->flags & X86_IRQ_ALLOC_LEGACY) {
apicd->vector = ISA_IRQ_VECTOR(virq + i);
apicd->cpu = 0;
trace_vector_setup(virq + i, true, 0);
raw_spin_lock_irqsave(&vector_lock, flags);
apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu);
raw_spin_unlock_irqrestore(&vector_lock, flags);
continue;
if (!vector_configure_legacy(virq + i, irqd, apicd))
continue;
}
err = assign_irq_vector_policy(irqd, info);