PCI: imx: enable imx8mm pcie support
Enable iMX8MM PCIe support. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>5.4-rM2-2.2.x-imx-squashed
Richard Zhu
Dong Aisheng
parent
b71e692290
commit
46a288f17b
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@ -51,6 +51,7 @@ enum imx6_pcie_variants {
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IMX6QP,
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IMX7D,
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IMX8MQ,
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IMX8MM,
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IMX8QM,
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IMX8QXP,
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};
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@ -167,6 +168,17 @@ struct imx6_pcie {
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#define PCIE_PHY_CMN_REG26 0x98
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#define PCIE_PHY_CMN_REG26_ATT_MODE 0xBC
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#define PCIE_PHY_CMN_REG62 0x188
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#define PCIE_PHY_CMN_REG62_PLL_CLK_OUT 0x08
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#define PCIE_PHY_CMN_REG64 0x190
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#define PCIE_PHY_CMN_REG64_AUX_RX_TX_TERM 0x8C
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#define PCIE_PHY_CMN_REG75 0x1D4
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#define PCIE_PHY_CMN_REG75_PLL_DONE 0x3
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#define PCIE_PHY_TRSV_REG5 0x414
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#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D
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#define PCIE_PHY_TRSV_REG6 0x418
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#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF
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#define PHY_RX_OVRD_IN_LO 0x1005
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#define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5)
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#define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3)
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@ -208,6 +220,14 @@ struct imx6_pcie {
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#define IMX8QM_MISC_PHYX1_EPCS_SEL BIT(12)
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#define IMX8QM_MISC_PCIE_AB_SELECT BIT(13)
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#define IMX8MM_GPR_PCIE_REF_CLK_SEL (0x3 << 24)
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#define IMX8MM_GPR_PCIE_REF_CLK_PLL (0x3 << 24)
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#define IMX8MM_GPR_PCIE_REF_CLK_EXT (0x2 << 24)
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#define IMX8MM_GPR_PCIE_AUX_EN BIT(19)
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#define IMX8MM_GPR_PCIE_CMN_RST BIT(18)
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#define IMX8MM_GPR_PCIE_POWER_OFF BIT(17)
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#define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
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static bool imx6_pcie_readable_reg(struct device *dev, unsigned int reg)
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{
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enum imx6_pcie_variants variant;
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@ -532,7 +552,6 @@ static int imx6_pcie_attach_pd(struct device *dev)
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static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
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{
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WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ);
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return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
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}
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@ -572,6 +591,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
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case IMX7D:
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break;
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case IMX8MQ:
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case IMX8MM:
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ret = clk_prepare_enable(imx6_pcie->pcie_aux);
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if (ret) {
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dev_err(dev, "unable to enable pcie_aux clock\n");
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@ -635,52 +655,64 @@ static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
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PHY_PLL_LOCK_WAIT_TIMEOUT))
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dev_err(dev, "PCIe PLL lock timeout\n");
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}
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static int imx8_hsio_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
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static void imx8_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
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{
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u32 val, retries = 0, tmp = 0, orig = 0;
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int ret;
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struct dw_pcie *pci = imx6_pcie->pci;
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struct device *dev = pci->dev;
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for (retries = 0; retries < PHY_PLL_LOCK_WAIT_MAX_RETRIES; retries++) {
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if (imx6_pcie->hsio_cfg == PCIEAX1PCIEBX1SATA) {
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regmap_read(imx6_pcie->iomuxc_gpr,
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IMX8QM_CSR_PHYX2_OFFSET + 0x4,
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&tmp);
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if (imx6_pcie->controller_id == 0) /* pciea 1 lanes */
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orig = IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
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else /* pcieb 1 lanes */
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orig = IMX8QM_STTS0_LANE1_TX_PLL_LOCK;
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} else if (imx6_pcie->hsio_cfg == PCIEAX2PCIEBX1) {
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val = IMX8QM_CSR_PHYX2_OFFSET
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+ imx6_pcie->controller_id * SZ_64K;
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regmap_read(imx6_pcie->iomuxc_gpr,
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val + IMX8QM_CSR_PHYX_STTS0_OFFSET,
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&tmp);
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orig = IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
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if (imx6_pcie->controller_id == 0) /* pciea 2 lanes */
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orig |= IMX8QM_STTS0_LANE1_TX_PLL_LOCK;
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} else if (imx6_pcie->hsio_cfg == PCIEAX2SATA) {
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regmap_read(imx6_pcie->iomuxc_gpr,
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IMX8QM_CSR_PHYX2_OFFSET + 0x4,
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&tmp);
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orig = IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
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orig |= IMX8QM_STTS0_LANE1_TX_PLL_LOCK;
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switch (imx6_pcie->drvdata->variant) {
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case IMX8MM:
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for (retries = 0; retries < PHY_PLL_LOCK_WAIT_MAX_RETRIES;
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retries++) {
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tmp = readl(imx6_pcie->phy_base + PCIE_PHY_CMN_REG75);
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if (tmp == PCIE_PHY_CMN_REG75_PLL_DONE)
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break;
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udelay(10);
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}
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tmp &= orig;
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if (tmp == orig)
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break;
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udelay(10);
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break;
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case IMX8QXP:
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case IMX8QM:
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for (retries = 0; retries < PHY_PLL_LOCK_WAIT_MAX_RETRIES;
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retries++) {
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if (imx6_pcie->hsio_cfg == PCIEAX1PCIEBX1SATA) {
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regmap_read(imx6_pcie->iomuxc_gpr,
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IMX8QM_CSR_PHYX2_OFFSET + 0x4,
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&tmp);
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if (imx6_pcie->controller_id == 0) /* pciea 1 lanes */
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orig = IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
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else /* pcieb 1 lanes */
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orig = IMX8QM_STTS0_LANE1_TX_PLL_LOCK;
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} else if (imx6_pcie->hsio_cfg == PCIEAX2PCIEBX1) {
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val = IMX8QM_CSR_PHYX2_OFFSET
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+ imx6_pcie->controller_id * SZ_64K;
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regmap_read(imx6_pcie->iomuxc_gpr,
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val + IMX8QM_CSR_PHYX_STTS0_OFFSET,
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&tmp);
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orig = IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
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if (imx6_pcie->controller_id == 0) /* pciea 2 lanes */
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orig |= IMX8QM_STTS0_LANE1_TX_PLL_LOCK;
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} else if (imx6_pcie->hsio_cfg == PCIEAX2SATA) {
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regmap_read(imx6_pcie->iomuxc_gpr,
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IMX8QM_CSR_PHYX2_OFFSET + 0x4,
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&tmp);
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orig = IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
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orig |= IMX8QM_STTS0_LANE1_TX_PLL_LOCK;
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}
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tmp &= orig;
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if (tmp == orig)
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break;
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udelay(10);
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}
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break;
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default:
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break;
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}
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if (retries >= PHY_PLL_LOCK_WAIT_MAX_RETRIES) {
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dev_info(dev, "pcie phy pll can't be locked.\n");
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ret = -ENODEV;
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} else {
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dev_info(dev, "pcie phy pll is locked.\n");
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}
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return ret;
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if (retries >= PHY_PLL_LOCK_WAIT_MAX_RETRIES)
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dev_err(dev, "PCIe PLL lock timeout\n");
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}
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static void imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie)
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@ -725,6 +757,7 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
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IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
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break;
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case IMX8MQ:
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case IMX8MM:
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clk_disable_unprepare(imx6_pcie->pcie_aux);
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break;
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case IMX8QXP:
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@ -748,6 +781,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
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switch (imx6_pcie->drvdata->variant) {
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case IMX7D:
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case IMX8MQ:
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case IMX8MM:
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reset_control_assert(imx6_pcie->pciephy_reset);
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reset_control_assert(imx6_pcie->apps_reset);
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break;
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@ -870,13 +904,13 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
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dev_err(dev, "ERROR PM_REQ_CORE_RST is still set.\n");
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/* wait for phy pll lock firstly. */
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if (imx8_hsio_pcie_wait_for_phy_pll_lock(imx6_pcie)) {
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ret = -ENODEV;
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goto err_pcie_phy;
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}
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imx8_pcie_wait_for_phy_pll_lock(imx6_pcie);
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break;
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case IMX8MQ:
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case IMX8MM:
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reset_control_deassert(imx6_pcie->pciephy_reset);
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imx8_pcie_wait_for_phy_pll_lock(imx6_pcie);
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break;
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case IMX7D:
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reset_control_deassert(imx6_pcie->pciephy_reset);
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@ -917,14 +951,6 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
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}
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return;
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err_pcie_phy:
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if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
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ret = regulator_disable(imx6_pcie->vpcie);
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if (ret)
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dev_err(dev, "failed to disable vpcie regulator: %d\n",
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ret);
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}
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}
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static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
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@ -956,6 +982,8 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
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static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
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{
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unsigned int offset;
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switch (imx6_pcie->drvdata->variant) {
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case IMX8QXP:
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case IMX8QM:
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@ -1049,6 +1077,73 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
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| IMX8QM_CSR_MISC_IOB_A_0_M1M0_2);
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}
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break;
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case IMX8MM:
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offset = imx6_pcie_grp_offset(imx6_pcie);
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dev_info(imx6_pcie->pci->dev, "%s REF_CLK is used!.\n",
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imx6_pcie->ext_osc ? "EXT" : "PLL");
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if (imx6_pcie->ext_osc) {
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regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
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IMX8MQ_GPR_PCIE_REF_USE_PAD, 0);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
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IMX8MM_GPR_PCIE_REF_CLK_SEL,
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IMX8MM_GPR_PCIE_REF_CLK_SEL);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
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IMX8MM_GPR_PCIE_AUX_EN,
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IMX8MM_GPR_PCIE_AUX_EN);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
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IMX8MM_GPR_PCIE_POWER_OFF, 0);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
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IMX8MM_GPR_PCIE_SSC_EN, 0);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
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IMX8MM_GPR_PCIE_REF_CLK_SEL,
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IMX8MM_GPR_PCIE_REF_CLK_EXT);
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udelay(100);
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/* Do the PHY common block reset */
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regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
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IMX8MM_GPR_PCIE_CMN_RST,
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IMX8MM_GPR_PCIE_CMN_RST);
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udelay(200);
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} else {
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/* Configure the internal PLL as REF clock */
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regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
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IMX8MQ_GPR_PCIE_REF_USE_PAD, 0);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
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IMX8MM_GPR_PCIE_REF_CLK_SEL,
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IMX8MM_GPR_PCIE_REF_CLK_SEL);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
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IMX8MM_GPR_PCIE_AUX_EN,
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IMX8MM_GPR_PCIE_AUX_EN);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
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IMX8MM_GPR_PCIE_POWER_OFF, 0);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
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IMX8MM_GPR_PCIE_SSC_EN, 0);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
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IMX8MM_GPR_PCIE_REF_CLK_SEL,
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IMX8MM_GPR_PCIE_REF_CLK_PLL);
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udelay(100);
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/* Configure the PHY */
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writel(PCIE_PHY_CMN_REG62_PLL_CLK_OUT,
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imx6_pcie->phy_base + PCIE_PHY_CMN_REG62);
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writel(PCIE_PHY_CMN_REG64_AUX_RX_TX_TERM,
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imx6_pcie->phy_base + PCIE_PHY_CMN_REG64);
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/* Do the PHY common block reset */
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regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
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IMX8MM_GPR_PCIE_CMN_RST,
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IMX8MM_GPR_PCIE_CMN_RST);
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udelay(200);
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}
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/*
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* In order to pass the compliance tests.
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* Configure the TRSV regiser of iMX8MM PCIe PHY.
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*/
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writel(PCIE_PHY_TRSV_REG5_GEN1_DEEMP,
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imx6_pcie->phy_base + PCIE_PHY_TRSV_REG5);
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writel(PCIE_PHY_TRSV_REG6_GEN2_DEEMP,
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imx6_pcie->phy_base + PCIE_PHY_TRSV_REG6);
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break;
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case IMX8MQ:
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/*
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@ -1179,6 +1274,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
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break;
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case IMX7D:
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case IMX8MQ:
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case IMX8MM:
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reset_control_deassert(imx6_pcie->apps_reset);
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break;
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case IMX8QXP:
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@ -1365,6 +1461,8 @@ static void imx6_pcie_ltssm_disable(struct device *dev)
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IMX6Q_GPR12_PCIE_CTL_2, 0);
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break;
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case IMX7D:
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case IMX8MQ:
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case IMX8MM:
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reset_control_assert(imx6_pcie->apps_reset);
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break;
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case IMX8QXP:
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@ -1615,6 +1713,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
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}
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break;
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case IMX8MQ:
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case IMX8MM:
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imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
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if (IS_ERR(imx6_pcie->pcie_aux)) {
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dev_err(dev, "pcie_aux clock source missing or invalid\n");
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@ -1789,6 +1888,9 @@ static const struct imx6_pcie_drvdata drvdata[] = {
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[IMX8MQ] = {
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.variant = IMX8MQ,
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},
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[IMX8MM] = {
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.variant = IMX8MM,
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},
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[IMX8QM] = {
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.variant = IMX8QM,
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.flags = IMX6_PCIE_FLAG_IMX6_CPU_ADDR_FIXUP,
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@ -1804,7 +1906,8 @@ static const struct of_device_id imx6_pcie_of_match[] = {
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{ .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
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{ .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
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{ .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
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{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], } ,
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{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
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{ .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
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{ .compatible = "fsl,imx8qm-pcie", .data = &drvdata[IMX8QM], },
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{ .compatible = "fsl,imx8qxp-pcie", .data = &drvdata[IMX8QXP], },
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{},
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