spi: fsl-espi: align register access with other drivers
Change register access to the method used in other drivers too. - use register names as in the chip spec for constants - avoid hard to read statements like __be32 __iomem *espi_mode = ®_base->mode - get rid of old powerpc-specific functions like in_8 In addition annotate reg_base in struct mpc8xxx_spi as __iomem. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>hifive-unleashed-5.1
Heiner Kallweit
Mark Brown
parent
35f5d71e38
commit
46afd38b7d
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@ -26,16 +26,15 @@
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#include "spi-fsl-lib.h"
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/* eSPI Controller registers */
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struct fsl_espi_reg {
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__be32 mode; /* 0x000 - eSPI mode register */
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__be32 event; /* 0x004 - eSPI event register */
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__be32 mask; /* 0x008 - eSPI mask register */
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__be32 command; /* 0x00c - eSPI command register */
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__be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
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__be32 receive; /* 0x014 - eSPI receive FIFO access register*/
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u8 res[8]; /* 0x018 - 0x01c reserved */
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__be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
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};
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#define ESPI_SPMODE 0x00 /* eSPI mode register */
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#define ESPI_SPIE 0x04 /* eSPI event register */
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#define ESPI_SPIM 0x08 /* eSPI mask register */
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#define ESPI_SPCOM 0x0c /* eSPI command register */
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#define ESPI_SPITF 0x10 /* eSPI transmit FIFO access register*/
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#define ESPI_SPIRF 0x14 /* eSPI receive FIFO access register*/
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#define ESPI_SPMODE0 0x20 /* eSPI cs0 mode register */
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#define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4)
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/* eSPI Controller mode register definitions */
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#define SPMODE_ENABLE (1 << 31)
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@ -77,6 +76,28 @@ struct fsl_espi_reg {
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#define AUTOSUSPEND_TIMEOUT 2000
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static inline u32 fsl_espi_read_reg(struct mpc8xxx_spi *mspi, int offset)
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{
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return ioread32be(mspi->reg_base + offset);
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}
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static inline u8 fsl_espi_read_reg8(struct mpc8xxx_spi *mspi, int offset)
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{
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return ioread8(mspi->reg_base + offset);
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}
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static inline void fsl_espi_write_reg(struct mpc8xxx_spi *mspi, int offset,
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u32 val)
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{
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iowrite32be(val, mspi->reg_base + offset);
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}
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static inline void fsl_espi_write_reg8(struct mpc8xxx_spi *mspi, int offset,
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u8 val)
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{
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iowrite8(val, mspi->reg_base + offset);
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}
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static void fsl_espi_copy_to_buf(struct spi_message *m,
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struct mpc8xxx_spi *mspi)
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{
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@ -133,9 +154,6 @@ static void fsl_espi_change_mode(struct spi_device *spi)
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{
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struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
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struct spi_mpc8xxx_cs *cs = spi->controller_state;
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struct fsl_espi_reg *reg_base = mspi->reg_base;
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__be32 __iomem *mode = ®_base->csmode[spi->chip_select];
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__be32 __iomem *espi_mode = ®_base->mode;
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u32 tmp;
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unsigned long flags;
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@ -143,10 +161,11 @@ static void fsl_espi_change_mode(struct spi_device *spi)
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local_irq_save(flags);
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/* Turn off SPI unit prior changing mode */
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tmp = mpc8xxx_spi_read_reg(espi_mode);
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mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
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mpc8xxx_spi_write_reg(mode, cs->hw_mode);
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mpc8xxx_spi_write_reg(espi_mode, tmp);
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tmp = fsl_espi_read_reg(mspi, ESPI_SPMODE);
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fsl_espi_write_reg(mspi, ESPI_SPMODE, tmp & ~SPMODE_ENABLE);
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fsl_espi_write_reg(mspi, ESPI_SPMODEx(spi->chip_select),
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cs->hw_mode);
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fsl_espi_write_reg(mspi, ESPI_SPMODE, tmp);
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local_irq_restore(flags);
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}
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@ -228,7 +247,6 @@ static void fsl_espi_setup_transfer(struct spi_device *spi,
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static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
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{
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struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
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struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
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u32 word;
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int ret;
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@ -241,15 +259,15 @@ static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
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reinit_completion(&mpc8xxx_spi->done);
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/* Set SPCOM[CS] and SPCOM[TRANLEN] field */
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mpc8xxx_spi_write_reg(®_base->command,
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fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM,
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(SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
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/* enable rx ints */
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mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
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fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, SPIM_NE);
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/* transmit word */
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word = mpc8xxx_spi->get_tx(mpc8xxx_spi);
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mpc8xxx_spi_write_reg(®_base->transmit, word);
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fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPITF, word);
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/* Won't hang up forever, SPI bus sometimes got lost interrupts... */
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ret = wait_for_completion_timeout(&mpc8xxx_spi->done, 2 * HZ);
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@ -259,7 +277,7 @@ static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
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mpc8xxx_spi->count);
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/* disable rx ints */
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mpc8xxx_spi_write_reg(®_base->mask, 0);
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fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0);
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return mpc8xxx_spi->count > 0 ? -EMSGSIZE : 0;
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}
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@ -329,7 +347,6 @@ out:
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static int fsl_espi_setup(struct spi_device *spi)
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{
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struct mpc8xxx_spi *mpc8xxx_spi;
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struct fsl_espi_reg *reg_base;
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u32 hw_mode;
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u32 loop_mode;
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struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
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@ -345,13 +362,12 @@ static int fsl_espi_setup(struct spi_device *spi)
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}
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mpc8xxx_spi = spi_master_get_devdata(spi->master);
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reg_base = mpc8xxx_spi->reg_base;
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pm_runtime_get_sync(mpc8xxx_spi->dev);
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hw_mode = cs->hw_mode; /* Save original settings */
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cs->hw_mode = mpc8xxx_spi_read_reg(
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®_base->csmode[spi->chip_select]);
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cs->hw_mode = fsl_espi_read_reg(mpc8xxx_spi,
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ESPI_SPMODEx(spi->chip_select));
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/* mask out bits we are going to set */
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cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
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| CSMODE_REV);
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@ -364,11 +380,11 @@ static int fsl_espi_setup(struct spi_device *spi)
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cs->hw_mode |= CSMODE_REV;
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/* Handle the loop mode */
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loop_mode = mpc8xxx_spi_read_reg(®_base->mode);
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loop_mode = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE);
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loop_mode &= ~SPMODE_LOOP;
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if (spi->mode & SPI_LOOP)
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loop_mode |= SPMODE_LOOP;
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mpc8xxx_spi_write_reg(®_base->mode, loop_mode);
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fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, loop_mode);
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fsl_espi_setup_transfer(spi, NULL);
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@ -388,8 +404,6 @@ static void fsl_espi_cleanup(struct spi_device *spi)
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static void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
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{
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struct fsl_espi_reg *reg_base = mspi->reg_base;
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/* We need handle RX first */
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if (events & SPIE_NE) {
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u32 rx_data, tmp;
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@ -401,7 +415,7 @@ static void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
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if (SPIE_RXCNT(events) < min(4, mspi->len)) {
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ret = spin_event_timeout(
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!(SPIE_RXCNT(events =
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mpc8xxx_spi_read_reg(®_base->event)) <
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fsl_espi_read_reg(mspi, ESPI_SPIE)) <
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min(4, mspi->len)),
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10000, 0); /* 10 msec */
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if (!ret)
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@ -410,7 +424,7 @@ static void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
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}
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if (mspi->len >= 4) {
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rx_data = mpc8xxx_spi_read_reg(®_base->receive);
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rx_data = fsl_espi_read_reg(mspi, ESPI_SPIRF);
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} else if (mspi->len <= 0) {
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dev_err(mspi->dev,
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"unexpected RX(SPIE_NE) interrupt occurred,\n"
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@ -422,7 +436,8 @@ static void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
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tmp = mspi->len;
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rx_data = 0;
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while (tmp--) {
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rx_data_8 = in_8((u8 *)®_base->receive);
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rx_data_8 = fsl_espi_read_reg8(mspi,
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ESPI_SPIRF);
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rx_data |= (rx_data_8 << (tmp * 8));
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}
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@ -439,8 +454,8 @@ static void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
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int ret;
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/* spin until TX is done */
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ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
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®_base->event)) & SPIE_NF), 1000, 0);
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ret = spin_event_timeout(((events = fsl_espi_read_reg(
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mspi, ESPI_SPIE)) & SPIE_NF), 1000, 0);
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if (!ret) {
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dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
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complete(&mspi->done);
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@ -452,7 +467,7 @@ static void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
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if (mspi->count) {
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u32 word = mspi->get_tx(mspi);
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mpc8xxx_spi_write_reg(®_base->transmit, word);
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fsl_espi_write_reg(mspi, ESPI_SPITF, word);
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} else {
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complete(&mspi->done);
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}
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@ -461,11 +476,10 @@ static void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
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static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
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{
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struct mpc8xxx_spi *mspi = context_data;
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struct fsl_espi_reg *reg_base = mspi->reg_base;
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u32 events;
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/* Get interrupt events(tx/rx) */
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events = mpc8xxx_spi_read_reg(®_base->event);
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events = fsl_espi_read_reg(mspi, ESPI_SPIE);
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if (!events)
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return IRQ_NONE;
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@ -474,7 +488,7 @@ static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
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fsl_espi_cpu_irq(mspi, events);
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/* Clear the events */
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mpc8xxx_spi_write_reg(®_base->event, events);
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fsl_espi_write_reg(mspi, ESPI_SPIE, events);
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return IRQ_HANDLED;
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}
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@ -484,12 +498,11 @@ static int fsl_espi_runtime_suspend(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
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struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
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u32 regval;
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regval = mpc8xxx_spi_read_reg(®_base->mode);
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regval = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE);
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regval &= ~SPMODE_ENABLE;
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mpc8xxx_spi_write_reg(®_base->mode, regval);
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fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval);
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return 0;
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}
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@ -498,12 +511,11 @@ static int fsl_espi_runtime_resume(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
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struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
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u32 regval;
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regval = mpc8xxx_spi_read_reg(®_base->mode);
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regval = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE);
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regval |= SPMODE_ENABLE;
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mpc8xxx_spi_write_reg(®_base->mode, regval);
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fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval);
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return 0;
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}
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@ -520,7 +532,6 @@ static struct spi_master * fsl_espi_probe(struct device *dev,
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struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
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struct spi_master *master;
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struct mpc8xxx_spi *mpc8xxx_spi;
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struct fsl_espi_reg *reg_base;
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struct device_node *nc;
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const __be32 *prop;
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u32 regval, csmode;
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@ -558,8 +569,6 @@ static struct spi_master * fsl_espi_probe(struct device *dev,
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goto err_probe;
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}
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reg_base = mpc8xxx_spi->reg_base;
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/* Register for SPI Interrupt */
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ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_espi_irq,
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0, "fsl_espi", mpc8xxx_spi);
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@ -572,10 +581,10 @@ static struct spi_master * fsl_espi_probe(struct device *dev,
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}
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/* SPI controller initializations */
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mpc8xxx_spi_write_reg(®_base->mode, 0);
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mpc8xxx_spi_write_reg(®_base->mask, 0);
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mpc8xxx_spi_write_reg(®_base->command, 0);
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mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
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fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, 0);
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fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0);
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fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, 0);
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fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIE, 0xffffffff);
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/* Init eSPI CS mode register */
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for_each_available_child_of_node(master->dev.of_node, nc) {
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@ -600,7 +609,7 @@ static struct spi_master * fsl_espi_probe(struct device *dev,
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csmode &= ~(CSMODE_AFT(0xf));
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csmode |= CSMODE_AFT(be32_to_cpup(prop));
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}
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mpc8xxx_spi_write_reg(®_base->csmode[i], csmode);
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fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODEx(i), csmode);
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dev_info(dev, "cs=%d, init_csmode=0x%x\n", i, csmode);
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}
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@ -608,7 +617,7 @@ static struct spi_master * fsl_espi_probe(struct device *dev,
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/* Enable SPI interface */
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regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
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mpc8xxx_spi_write_reg(®_base->mode, regval);
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fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval);
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pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT);
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pm_runtime_use_autosuspend(dev);
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@ -620,7 +629,8 @@ static struct spi_master * fsl_espi_probe(struct device *dev,
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if (ret < 0)
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goto err_pm;
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dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
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dev_info(dev, "at 0x%p (irq = %d)\n", mpc8xxx_spi->reg_base,
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mpc8xxx_spi->irq);
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pm_runtime_mark_last_busy(dev);
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pm_runtime_put_autosuspend(dev);
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@ -726,27 +736,26 @@ static int of_fsl_espi_resume(struct device *dev)
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struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
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struct spi_master *master = dev_get_drvdata(dev);
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struct mpc8xxx_spi *mpc8xxx_spi;
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struct fsl_espi_reg *reg_base;
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u32 regval;
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int i, ret;
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mpc8xxx_spi = spi_master_get_devdata(master);
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reg_base = mpc8xxx_spi->reg_base;
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/* SPI controller initializations */
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mpc8xxx_spi_write_reg(®_base->mode, 0);
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mpc8xxx_spi_write_reg(®_base->mask, 0);
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mpc8xxx_spi_write_reg(®_base->command, 0);
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mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
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fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, 0);
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fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0);
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fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, 0);
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fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIE, 0xffffffff);
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/* Init eSPI CS mode register */
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for (i = 0; i < pdata->max_chipselect; i++)
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mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL);
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fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODEx(i),
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CSMODE_INIT_VAL);
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/* Enable SPI interface */
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regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
|
||||
|
||||
mpc8xxx_spi_write_reg(®_base->mode, regval);
|
||||
fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval);
|
||||
|
||||
ret = pm_runtime_force_resume(dev);
|
||||
if (ret < 0)
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
/* SPI/eSPI Controller driver's private data. */
|
||||
struct mpc8xxx_spi {
|
||||
struct device *dev;
|
||||
void *reg_base;
|
||||
void __iomem *reg_base;
|
||||
|
||||
/* rx & tx bufs from the spi_transfer */
|
||||
const void *tx;
|
||||
|
|
|
|||
Loading…
Reference in New Issue