drm/i915: metadata for shared dplls
An id to match the idx (useful for register access macros) and a name fore neater debug output. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -132,15 +132,6 @@ enum hpd_pin {
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list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
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if ((intel_encoder)->base.crtc == (__crtc))
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struct intel_shared_dpll {
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int refcount; /* count of number of CRTCs sharing this PLL */
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int active; /* count of number of active CRTCs (i.e. DPMS on) */
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bool on; /* is the PLL actually active? Disabled during modeset */
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int pll_reg;
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int fp0_reg;
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int fp1_reg;
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};
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enum intel_dpll_id {
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DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
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/* real shared dpll ids must be >= 0 */
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@ -149,6 +140,18 @@ enum intel_dpll_id {
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};
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#define I915_NUM_PLLS 2
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struct intel_shared_dpll {
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int refcount; /* count of number of CRTCs sharing this PLL */
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int active; /* count of number of active CRTCs (i.e. DPMS on) */
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bool on; /* is the PLL actually active? Disabled during modeset */
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const char *name;
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/* should match the index in the dev_priv->shared_dplls array */
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enum intel_dpll_id id;
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int pll_reg;
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int fp0_reg;
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int fp1_reg;
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};
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/* Used by dp and fdi links */
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struct intel_link_m_n {
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uint32_t tu;
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@ -935,14 +935,14 @@ static void assert_shared_dpll(struct drm_i915_private *dev_priv,
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}
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if (WARN (!pll,
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"asserting PCH PLL %s with no PLL\n", state_string(state)))
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"asserting DPLL %s with no DPLL\n", state_string(state)))
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return;
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val = I915_READ(pll->pll_reg);
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cur_state = !!(val & DPLL_VCO_ENABLE);
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WARN(cur_state != state,
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"PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
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pll->pll_reg, state_string(state), state_string(cur_state), val);
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"%s assertion failure (expected %s, current %s), val=%08x\n",
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pll->name, state_string(state), state_string(cur_state), val);
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/* Make sure the selected PLL is correctly attached to the transcoder */
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if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
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@ -1430,8 +1430,8 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
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if (WARN_ON(pll->refcount == 0))
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return;
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DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
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pll->pll_reg, pll->active, pll->on,
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DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
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pll->name, pll->active, pll->on,
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crtc->base.base.id);
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/* PCH refclock must be enabled first */
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@ -1444,7 +1444,7 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
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}
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WARN_ON(pll->on);
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DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
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DRM_DEBUG_KMS("enabling %s\n", pll->name);
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reg = pll->pll_reg;
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val = I915_READ(reg);
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@ -1471,8 +1471,8 @@ static void intel_disable_shared_dpll(struct intel_crtc *crtc)
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if (WARN_ON(pll->refcount == 0))
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return;
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DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
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pll->pll_reg, pll->active, pll->on,
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DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
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pll->name, pll->active, pll->on,
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crtc->base.base.id);
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if (WARN_ON(pll->active == 0)) {
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@ -1485,7 +1485,7 @@ static void intel_disable_shared_dpll(struct intel_crtc *crtc)
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if (--pll->active)
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return;
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DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
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DRM_DEBUG_KMS("disabling %s\n", pll->name);
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/* Make sure transcoder isn't still depending on us */
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assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
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@ -3065,7 +3065,7 @@ static void intel_put_shared_dpll(struct intel_crtc *crtc)
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return;
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if (pll->refcount == 0) {
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WARN(1, "bad PCH PLL refcount\n");
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WARN(1, "bad %s refcount\n", pll->name);
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return;
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}
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@ -3084,8 +3084,8 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
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enum intel_dpll_id i;
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if (pll) {
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DRM_DEBUG_KMS("CRTC:%d dropping existing PCH PLL %x\n",
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crtc->base.base.id, pll->pll_reg);
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DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
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crtc->base.base.id, pll->name);
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intel_put_shared_dpll(crtc);
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}
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@ -3094,8 +3094,8 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
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i = crtc->pipe;
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pll = &dev_priv->shared_dplls[i];
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DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
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crtc->base.base.id, pll->pll_reg);
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DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
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crtc->base.base.id, pll->name);
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goto found;
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}
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@ -3109,9 +3109,9 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
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if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
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fp == I915_READ(pll->fp0_reg)) {
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DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
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DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
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crtc->base.base.id,
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pll->pll_reg, pll->refcount, pll->active);
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pll->name, pll->refcount, pll->active);
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goto found;
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}
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@ -3121,8 +3121,8 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
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for (i = 0; i < dev_priv->num_shared_dpll; i++) {
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pll = &dev_priv->shared_dplls[i];
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if (pll->refcount == 0) {
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DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
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crtc->base.base.id, pll->pll_reg);
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DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
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crtc->base.base.id, pll->name);
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goto found;
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}
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}
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@ -3131,9 +3131,10 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
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found:
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crtc->config.shared_dpll = i;
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DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(crtc->pipe));
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DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
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pipe_name(crtc->pipe));
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if (pll->active == 0) {
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DRM_DEBUG_DRIVER("setting up pll %d\n", i);
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DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
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WARN_ON(pll->on);
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assert_shared_dpll_disabled(dev_priv, pll, NULL);
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@ -8728,6 +8729,11 @@ static void intel_cpu_pll_init(struct drm_device *dev)
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intel_ddi_pll_init(dev);
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}
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static char *ibx_pch_dpll_names[] = {
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"PCH DPLL A",
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"PCH DPLL B",
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};
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static void ibx_pch_dpll_init(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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@ -8736,6 +8742,8 @@ static void ibx_pch_dpll_init(struct drm_device *dev)
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dev_priv->num_shared_dpll = 2;
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for (i = 0; i < dev_priv->num_shared_dpll; i++) {
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dev_priv->shared_dplls[i].id = i;
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dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
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dev_priv->shared_dplls[i].pll_reg = _PCH_DPLL(i);
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dev_priv->shared_dplls[i].fp0_reg = _PCH_FP0(i);
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dev_priv->shared_dplls[i].fp1_reg = _PCH_FP1(i);
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