OMAP3: PM: Remove un-necessary cp15 registers form low power cpu context
The current code saves few un-necessary registers which are read-only or write-only, unused CP15 registers. Remove them and keep only necessary CP15 registers part of low power context save/restore. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>hifive-unleashed-5.1
Santosh Shilimkar
Kevin Hilman
parent
c9749a3523
commit
46f557cb45
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@ -214,66 +214,29 @@ save_context_wfi:
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beq clean_caches
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l1_logic_lost:
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/* Store sp and spsr to SDRAM */
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mov r4, sp
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mrs r5, spsr
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mov r6, lr
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mov r4, sp @ Store sp
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mrs r5, spsr @ Store spsr
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mov r6, lr @ Store lr
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stmia r8!, {r4-r6}
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/* Save all ARM registers */
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/* Coprocessor access control register */
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mrc p15, 0, r6, c1, c0, 2
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stmia r8!, {r6}
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/* TTBR0, TTBR1 and Translation table base control */
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mrc p15, 0, r4, c2, c0, 0
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mrc p15, 0, r5, c2, c0, 1
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mrc p15, 0, r6, c2, c0, 2
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stmia r8!, {r4-r6}
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/*
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* Domain access control register, data fault status register,
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* and instruction fault status register
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*/
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mrc p15, 0, r4, c3, c0, 0
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mrc p15, 0, r5, c5, c0, 0
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mrc p15, 0, r6, c5, c0, 1
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stmia r8!, {r4-r6}
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/*
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* Data aux fault status register, instruction aux fault status,
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* data fault address register and instruction fault address register
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*/
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mrc p15, 0, r4, c5, c1, 0
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mrc p15, 0, r5, c5, c1, 1
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mrc p15, 0, r6, c6, c0, 0
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mrc p15, 0, r7, c6, c0, 2
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stmia r8!, {r4-r7}
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/*
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* user r/w thread and process ID, user r/o thread and process ID,
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* priv only thread and process ID, cache size selection
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*/
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mrc p15, 0, r4, c13, c0, 2
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mrc p15, 0, r5, c13, c0, 3
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mrc p15, 0, r6, c13, c0, 4
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mrc p15, 2, r7, c0, c0, 0
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stmia r8!, {r4-r7}
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/* Data TLB lockdown, instruction TLB lockdown registers */
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mrc p15, 0, r5, c10, c0, 0
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mrc p15, 0, r6, c10, c0, 1
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stmia r8!, {r5-r6}
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/* Secure or non secure vector base address, FCSE PID, Context PID*/
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mrc p15, 0, r4, c12, c0, 0
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mrc p15, 0, r5, c13, c0, 0
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mrc p15, 0, r6, c13, c0, 1
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stmia r8!, {r4-r6}
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/* Primary remap, normal remap registers */
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mrc p15, 0, r4, c10, c2, 0
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mrc p15, 0, r5, c10, c2, 1
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stmia r8!,{r4-r5}
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/* Store current cpsr*/
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mrs r2, cpsr
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stmia r8!, {r2}
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mrc p15, 0, r4, c1, c0, 2 @ Coprocessor access control register
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mrc p15, 0, r5, c2, c0, 0 @ TTBR0
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mrc p15, 0, r6, c2, c0, 1 @ TTBR1
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mrc p15, 0, r7, c2, c0, 2 @ TTBCR
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stmia r8!, {r4-r7}
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mrc p15, 0, r4, c1, c0, 0
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/* save control register */
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mrc p15, 0, r4, c3, c0, 0 @ Domain access Control Register
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mrc p15, 0, r5, c10, c2, 0 @ PRRR
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mrc p15, 0, r6, c10, c2, 1 @ NMRR
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stmia r8!,{r4-r6}
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mrc p15, 0, r4, c13, c0, 1 @ Context ID
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mrc p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
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mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
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mrs r7, cpsr @ Store current cpsr
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stmia r8!, {r4-r7}
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mrc p15, 0, r4, c1, c0, 0 @ save control register
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stmia r8!, {r4}
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clean_caches:
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@ -489,68 +452,29 @@ skipl2reen:
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ldr r4, scratchpad_base
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ldr r3, [r4,#0xBC]
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adds r3, r3, #16
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ldmia r3!, {r4-r6}
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mov sp, r4
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msr spsr_cxsf, r5
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mov lr, r6
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mov sp, r4 @ Restore sp
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msr spsr_cxsf, r5 @ Restore spsr
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mov lr, r6 @ Restore lr
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ldmia r3!, {r4-r9}
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/* Coprocessor access Control Register */
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mcr p15, 0, r4, c1, c0, 2
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ldmia r3!, {r4-r7}
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mcr p15, 0, r4, c1, c0, 2 @ Coprocessor access Control Register
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mcr p15, 0, r5, c2, c0, 0 @ TTBR0
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mcr p15, 0, r6, c2, c0, 1 @ TTBR1
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mcr p15, 0, r7, c2, c0, 2 @ TTBCR
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ldmia r3!,{r4-r6}
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mcr p15, 0, r4, c3, c0, 0 @ Domain access Control Register
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mcr p15, 0, r5, c10, c2, 0 @ PRRR
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mcr p15, 0, r6, c10, c2, 1 @ NMRR
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/* TTBR0 */
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MCR p15, 0, r5, c2, c0, 0
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/* TTBR1 */
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MCR p15, 0, r6, c2, c0, 1
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/* Translation table base control register */
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MCR p15, 0, r7, c2, c0, 2
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/* Domain access Control Register */
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MCR p15, 0, r8, c3, c0, 0
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/* Data fault status Register */
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MCR p15, 0, r9, c5, c0, 0
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ldmia r3!,{r4-r8}
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/* Instruction fault status Register */
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MCR p15, 0, r4, c5, c0, 1
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/* Data Auxiliary Fault Status Register */
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MCR p15, 0, r5, c5, c1, 0
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/* Instruction Auxiliary Fault Status Register*/
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MCR p15, 0, r6, c5, c1, 1
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/* Data Fault Address Register */
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MCR p15, 0, r7, c6, c0, 0
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/* Instruction Fault Address Register*/
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MCR p15, 0, r8, c6, c0, 2
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ldmia r3!,{r4-r7}
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/* User r/w thread and process ID */
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MCR p15, 0, r4, c13, c0, 2
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/* User ro thread and process ID */
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MCR p15, 0, r5, c13, c0, 3
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/* Privileged only thread and process ID */
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MCR p15, 0, r6, c13, c0, 4
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/* Cache size selection */
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MCR p15, 2, r7, c0, c0, 0
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ldmia r3!,{r4-r8}
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/* Data TLB lockdown registers */
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MCR p15, 0, r4, c10, c0, 0
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/* Instruction TLB lockdown registers */
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MCR p15, 0, r5, c10, c0, 1
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/* Secure or Nonsecure Vector Base Address */
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MCR p15, 0, r6, c12, c0, 0
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/* FCSE PID */
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MCR p15, 0, r7, c13, c0, 0
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/* Context PID */
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MCR p15, 0, r8, c13, c0, 1
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ldmia r3!,{r4-r5}
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/* Primary memory remap register */
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MCR p15, 0, r4, c10, c2, 0
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/* Normal memory remap register */
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MCR p15, 0, r5, c10, c2, 1
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/* Restore cpsr */
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ldmia r3!,{r4} @ load CPSR from SDRAM
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msr cpsr, r4 @ store cpsr
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mcr p15, 0, r4, c13, c0, 1 @ Context ID
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mcr p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
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mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
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msr cpsr, r7 @ store cpsr
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/* Enabling MMU here */
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mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl
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