From 46fe72556efe672c53fd593c44036550a91ce0c3 Mon Sep 17 00:00:00 2001 From: Stefan-Gabriel Mirea Date: Wed, 16 Aug 2017 14:53:25 +0100 Subject: [PATCH] dt-bindings: clock: Document S32V234 MC_CGM and MC_ME Add DT bindings documentation for the upcoming S32V234 clk driver. Add s32v234-clock.h header, which is referred in MC_CGM documentation. Signed-off-by: Stoica Cosmin-Stefan Signed-off-by: Stefan-Gabriel Mirea --- .../bindings/clock/s32v234-mc_cgm.txt | 31 +++++++++++++++++++ .../bindings/clock/s32v234-mc_me.txt | 16 ++++++++++ include/dt-bindings/clock/s32v234-clock.h | 22 +++++++++++++ 3 files changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/s32v234-mc_cgm.txt create mode 100644 Documentation/devicetree/bindings/clock/s32v234-mc_me.txt create mode 100644 include/dt-bindings/clock/s32v234-clock.h diff --git a/Documentation/devicetree/bindings/clock/s32v234-mc_cgm.txt b/Documentation/devicetree/bindings/clock/s32v234-mc_cgm.txt new file mode 100644 index 000000000000..d0d43e6ae597 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/s32v234-mc_cgm.txt @@ -0,0 +1,31 @@ +* NXP S32V234 Clock Generation Modules (MC_CGMs) + +The SoC supports four Clock Generation Modules, which provide registers for +system and peripherals clock source selection and division. See chapters 22 +("Clocking"), 23 ("Clock Generation Module (MC_CGM)") and 69 ("Mode Entry +Module (MC_ME)") in the reference manual[1]. + +This binding uses the common clock binding: + Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible: + Should be: + - "fsl,s32v234-mc_cgm0" for MC_CGM_0 + - "fsl,s32v234-mc_cgm1" for MC_CGM_1 + - "fsl,s32v234-mc_cgm2" for MC_CGM_2 + - "fsl,s32v234-mc_cgm3" for MC_CGM_3 +- reg: + Location and length of the register set +- #clock-cells (only for MC_CGM_0): + Should be <1>. See dt-bindings/clock/s32v234-clock.h for the clock + specifiers allowed in the clocks property of consumers. + +Example: +clks: mc_cgm0@4003c000 { + compatible = "fsl,s32v234-mc_cgm0"; + reg = <0x0 0x4003C000 0x0 0x1000>; + #clock-cells = <1>; +}; + +[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM diff --git a/Documentation/devicetree/bindings/clock/s32v234-mc_me.txt b/Documentation/devicetree/bindings/clock/s32v234-mc_me.txt new file mode 100644 index 000000000000..e9f4dcc3a257 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/s32v234-mc_me.txt @@ -0,0 +1,16 @@ +* NXP S32V234 Mode Entry Module (MC_ME) + +See chapters 22 ("Clocking") and 69 ("Mode Entry Module (MC_ME)") in the +reference manual[1]. + +Required properties: +- compatible: Should be "fsl,s32v234-mc_me" +- reg: Location and length of the register set + +Example: +mc_me: mc_me@4004a000 { + compatible = "fsl,s32v234-mc_me"; + reg = <0x0 0x4004A000 0x0 0x1000>; +}; + +[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM diff --git a/include/dt-bindings/clock/s32v234-clock.h b/include/dt-bindings/clock/s32v234-clock.h new file mode 100644 index 000000000000..c0ce57f9471a --- /dev/null +++ b/include/dt-bindings/clock/s32v234-clock.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright (C) 2017 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_S32V234_H +#define __DT_BINDINGS_CLOCK_S32V234_H + +#define S32V234_CLK_DUMMY 0 +#define S32V234_CLK_FXOSC 1 +#define S32V234_CLK_FIRC 2 +/* PERIPH PLL */ +#define S32V234_CLK_PERIPHPLL_SRC_SEL 3 +#define S32V234_CLK_PERIPHPLL_VCO 4 +#define S32V234_CLK_PERIPHPLL_PHI0 5 +#define S32V234_CLK_PERIPHPLL_PHI0_DIV3 6 +#define S32V234_CLK_PERIPHPLL_PHI0_DIV5 7 +#define S32V234_CLK_PERIPHPLL_PHI1 8 + +#define S32V234_CLK_END 9 +#endif /* __DT_BINDINGS_CLOCK_S32V234_H */