Pin control fixes for v5.4:
- Fix glitch risks in the Intel GPIO - Fix the Intel Cherryview valid irq mask calculation. - Allocate the Intel Cherryview irqchip dynamically. - Fix the valid mask init sequency on the ST STMFX driver. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAl3HVugACgkQQRCzN7AZ XXNcOw//UAEO6DnTc4+fr46Al4hsgShxlHk0URPEkMWZI7t+R6bs9icGGDOoejWS n7/Fpd7ChpYqtsRQD4sc1/hJwXxoUJFX0xzP7dI/PmT+st0OULAHjokoqK3RtERe 1shwAQq1NosIlwmsy+ZOqQwXUfq6RAnnVPblt6+VeG7Sc9bNHnDcg7d58GVFl7C3 S6D2v59pPMAL9JU+hQDQ8DiODXLk2k9k7Vtoq8bYLei0PMKdt/7I1kJjELPfghiA PMLmtTztygB27fUiFVVGVcCtaivLXqtI83yi9uYnY2rQ4Oa+zxuuej5rUL+TwybK P+XKJDNUeg/l6+wdkQXN8rJXkEXcU+Sms0HZmaYkML4l/6Oh4JtjDhij1KPqNjhY ufO7mnf2zkfooLD8rv9YC50yYKX3vZT4b5SrPnvd4lG2/C3hiZozwmAXdYtLgoqS BU9c2kfzIKHiFgBCJCnkyDesaGCfbkw5rDh1R4tSpABbShS242EdAYL0ZCuzjEsc 9iR4Jbi03mhCINjkFDbx5PnAZk8cJUeSmKFeWxDuZoUh3gU0VoPHlH533k6FsnLG Kck2sBPhpPRl/b/64jF21UDI1g3W0gxQet+hGCSYzcA/QQ0fo5+VKpGyTSvxzDnl LcbccAELH3qdzMDajtyEXaIeOv8huG9iBzS0pUibLbAsPqqrMhk= =fkcG -----END PGP SIGNATURE----- Merge tag 'pinctrl-v5.4-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control fixes from Linus Walleij: - Fix glitch risks in the Intel GPIO - Fix the Intel Cherryview valid irq mask calculation. - Allocate the Intel Cherryview irqchip dynamically. - Fix the valid mask init sequency on the ST STMFX driver. * tag 'pinctrl-v5.4-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: stmfx: fix valid_mask init sequence pinctrl: cherryview: Allocate IRQ chip dynamic pinctrl: cherryview: Fix irq_valid_mask calculation pinctrl: intel: Avoid potential glitches if pin is in GPIO modealistair/sunxi64-5.4-dsi
Linus Torvalds
commit
4763c0894a
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@ -147,6 +147,7 @@ struct chv_pin_context {
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* @pctldesc: Pin controller description
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* @pctldev: Pointer to the pin controller device
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* @chip: GPIO chip in this pin controller
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* @irqchip: IRQ chip in this pin controller
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* @regs: MMIO registers
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* @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
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* offset (in GPIO number space)
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@ -162,6 +163,7 @@ struct chv_pinctrl {
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struct pinctrl_desc pctldesc;
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struct pinctrl_dev *pctldev;
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struct gpio_chip chip;
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struct irq_chip irqchip;
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void __iomem *regs;
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unsigned intr_lines[16];
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const struct chv_community *community;
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@ -1466,16 +1468,6 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
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return 0;
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}
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static struct irq_chip chv_gpio_irqchip = {
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.name = "chv-gpio",
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.irq_startup = chv_gpio_irq_startup,
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.irq_ack = chv_gpio_irq_ack,
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.irq_mask = chv_gpio_irq_mask,
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.irq_unmask = chv_gpio_irq_unmask,
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.irq_set_type = chv_gpio_irq_type,
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.flags = IRQCHIP_SKIP_SET_WAKE,
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};
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static void chv_gpio_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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@ -1559,7 +1551,7 @@ static void chv_init_irq_valid_mask(struct gpio_chip *chip,
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intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
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if (intsel >= community->nirqs)
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clear_bit(i, valid_mask);
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clear_bit(desc->number, valid_mask);
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}
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}
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@ -1625,7 +1617,15 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
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}
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}
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ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0,
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pctrl->irqchip.name = "chv-gpio";
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pctrl->irqchip.irq_startup = chv_gpio_irq_startup;
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pctrl->irqchip.irq_ack = chv_gpio_irq_ack;
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pctrl->irqchip.irq_mask = chv_gpio_irq_mask;
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pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask;
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pctrl->irqchip.irq_set_type = chv_gpio_irq_type;
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pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE;
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ret = gpiochip_irqchip_add(chip, &pctrl->irqchip, 0,
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handle_bad_irq, IRQ_TYPE_NONE);
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if (ret) {
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dev_err(pctrl->dev, "failed to add IRQ chip\n");
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@ -1642,7 +1642,7 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
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}
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}
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gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq,
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gpiochip_set_chained_irqchip(chip, &pctrl->irqchip, irq,
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chv_gpio_irq_handler);
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return 0;
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}
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@ -52,6 +52,7 @@
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#define PADCFG0_GPIROUTNMI BIT(17)
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#define PADCFG0_PMODE_SHIFT 10
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#define PADCFG0_PMODE_MASK GENMASK(13, 10)
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#define PADCFG0_PMODE_GPIO 0
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#define PADCFG0_GPIORXDIS BIT(9)
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#define PADCFG0_GPIOTXDIS BIT(8)
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#define PADCFG0_GPIORXSTATE BIT(1)
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@ -332,7 +333,7 @@ static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
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cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
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mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
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if (!mode)
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if (mode == PADCFG0_PMODE_GPIO)
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seq_puts(s, "GPIO ");
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else
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seq_printf(s, "mode %d ", mode);
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@ -458,6 +459,11 @@ static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
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writel(value, padcfg0);
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}
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static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
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{
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return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
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}
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static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
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{
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u32 value;
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@ -491,7 +497,20 @@ static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
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}
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padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
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/*
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* If pin is already configured in GPIO mode, we assume that
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* firmware provides correct settings. In such case we avoid
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* potential glitches on the pin. Otherwise, for the pin in
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* alternative mode, consumer has to supply respective flags.
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*/
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if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) {
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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return 0;
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}
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intel_gpio_set_gpio_mode(padcfg0);
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/* Disable TX buffer and enable RX (this will be input) */
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__intel_gpio_set_direction(padcfg0, true);
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@ -585,19 +585,6 @@ static int stmfx_pinctrl_gpio_function_enable(struct stmfx_pinctrl *pctl)
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return stmfx_function_enable(pctl->stmfx, func);
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}
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static int stmfx_pinctrl_gpio_init_valid_mask(struct gpio_chip *gc,
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unsigned long *valid_mask,
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unsigned int ngpios)
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{
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struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
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u32 n;
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for_each_clear_bit(n, &pctl->gpio_valid_mask, ngpios)
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clear_bit(n, valid_mask);
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return 0;
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}
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static int stmfx_pinctrl_probe(struct platform_device *pdev)
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{
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struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent);
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@ -660,7 +647,6 @@ static int stmfx_pinctrl_probe(struct platform_device *pdev)
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pctl->gpio_chip.ngpio = pctl->pctl_desc.npins;
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pctl->gpio_chip.can_sleep = true;
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pctl->gpio_chip.of_node = np;
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pctl->gpio_chip.init_valid_mask = stmfx_pinctrl_gpio_init_valid_mask;
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ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl);
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if (ret) {
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Reference in New Issue