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drm/amd/display: Hook DCN2 into amdgpu_dm and expose as config (v2) 

Enable DCN2 support in DM (Display Manager).

v2: fix spurious raven change (Alex)

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
alistair/sunxi64-5.4-dsi
Harry Wentland 2019-02-22 16:52:52 -05:00 committed by Alex Deucher
parent 5b1b2f209f
commit 476e955dd6
3 changed files with 24 additions and 1 deletions
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9
drivers/gpu/drm/amd/display/Kconfig
View File

@ -16,6 +16,15 @@ config DRM_AMD_DC_DCN1_0
help
RV family support for display engine
config DRM_AMD_DC_DCN2_0
bool "DCN 2.0 family"
default y
depends on DRM_AMD_DC && X86
depends on DRM_AMD_DC_DCN1_0
help
Choose this option if you want to have
Navi support for display engine
config DEBUG_KERNEL_DC
bool "Enable kgdb break in DC"
depends on DRM_AMD_DC

14
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View File

@ -666,6 +666,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_VEGA20:
case CHIP_NAVI10:
return 0;
case CHIP_RAVEN:
if (ASICREV_IS_PICASSO(adev->external_rev_id))
@ -2210,6 +2211,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
break;
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN:
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
case CHIP_NAVI10:
#endif
if (dcn10_register_irq_handlers(dm->adev)) {
DRM_ERROR("DM: Failed to initialize IRQ\n");
goto fail;
@ -2362,6 +2366,13 @@ static int dm_early_init(void *handle)
adev->mode_info.num_hpd = 4;
adev->mode_info.num_dig = 4;
break;
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
case CHIP_NAVI10:
adev->mode_info.num_crtc = 6;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
break;
#endif
default:
DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
@ -2655,6 +2666,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
if (adev->asic_type == CHIP_VEGA10 ||
adev->asic_type == CHIP_VEGA12 ||
adev->asic_type == CHIP_VEGA20 ||
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
adev->asic_type == CHIP_NAVI10 ||
#endif
adev->asic_type == CHIP_RAVEN) {
/* Fill GFX9 params */
tiling_info->gfx9.num_pipes =

2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
View File

@ -166,7 +166,7 @@ int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc)
*/
stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS;
ret = mod_color_calculate_regamma_params(stream->out_transfer_func,
gamma, true, adev->asic_type <= CHIP_RAVEN, NULL);
gamma, true, adev->asic_type <= CHIP_NAVI10, NULL);
if (gamma)
dc_gamma_release(&gamma);