usb: dwc2/s3c-hsotg: move s3c-hsotg into dwc2 directory
Moves the s3c-hsotg driver into the dwc2 directory and uses the dwc2 defines in hw.h. Renames s3c-hsotg.c to gadget.c. NOTE: You can build both host and peripheral as a dynamically linked module, but be aware that if you insmod dwc2_gadget, then rmmod it, then insmod dwc2 and dwc2_platform for host mode, this will not work. As the step to rmmod dwc2_gadget.ko will turn off the clock to the USB IP. The dwc2 host driver currently does not look to turn on a clock yet. A patch to fix that will be coming soon. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> [ jh,rb - For gadget part only: ] Tested-by: Jingoo Han <jg1.han@samsung.com> Tested-by: Robert Baldyga <r.baldyga@samsung.com> [ pz: Folded Kconfig/Makefile changes, which were originally in a separate patch, into this one, to avoid a build breakage. Modified Kconfig/Makefile changes a bit. Tested host part only. ] Signed-off-by: Paul Zimmerman <paulz@synopsys.com> Acked-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Dinh Nguyen
Greg Kroah-Hartman
parent
6ab5332449
commit
47a1685f13
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@ -1,25 +1,58 @@
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config USB_DWC2
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tristate "DesignWare USB2 DRD Core Support"
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bool "DesignWare USB2 DRD Core Support"
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depends on USB
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help
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Say Y or M here if your system has a Dual Role HighSpeed
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USB controller based on the DesignWare HSOTG IP Core.
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Say Y here if your system has a Dual Role Hi-Speed USB
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controller based on the DesignWare HSOTG IP Core.
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If you choose to build this driver as dynamically linked
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modules, the core module will be called dwc2.ko, the
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PCI bus interface module (if you have a PCI bus system)
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will be called dwc2_pci.ko and the platform interface module
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(for controllers directly connected to the CPU) will be called
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dwc2_platform.ko.
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For host mode, if you choose to build the driver as dynamically
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linked modules, the core module will be called dwc2.ko, the PCI
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bus interface module (if you have a PCI bus system) will be
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called dwc2_pci.ko, and the platform interface module (for
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controllers directly connected to the CPU) will be called
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dwc2_platform.ko. For gadget mode, there will be a single
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module called dwc2_gadget.ko.
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NOTE: This driver at present only implements the Host mode
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of the controller. The existing s3c-hsotg driver supports
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Peripheral mode, but only for the Samsung S3C platforms.
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There are plans to merge the s3c-hsotg driver with this
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driver in the near future to create a dual-role driver.
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NOTE: The s3c-hsotg driver is now renamed to dwc2_gadget. The
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host and gadget drivers are still currently separate drivers.
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There are plans to merge the dwc2_gadget driver with the dwc2
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host driver in the near future to create a dual-role driver.
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if USB_DWC2
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config USB_DWC2_HOST
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tristate "Host only mode"
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depends on USB
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help
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The Designware USB2.0 high-speed host controller
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integrated into many SoCs.
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config USB_DWC2_PLATFORM
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bool "DWC2 Platform"
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depends on USB_DWC2_HOST
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default USB_DWC2_HOST
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help
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The Designware USB2.0 platform interface module for
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controllers directly connected to the CPU. This is only
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used for host mode.
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config USB_DWC2_PCI
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bool "DWC2 PCI"
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depends on USB_DWC2_HOST && PCI
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default USB_DWC2_HOST
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help
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The Designware USB2.0 PCI interface module for controllers
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connected to a PCI bus. This is only used for host mode.
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comment "Gadget mode requires USB Gadget support to be enabled"
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config USB_DWC2_PERIPHERAL
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tristate "Gadget only mode"
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depends on USB_GADGET
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help
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The Designware USB2.0 high-speed gadget controller
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integrated into many SoCs.
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config USB_DWC2_DEBUG
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bool "Enable Debugging Messages"
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help
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@ -1,25 +1,28 @@
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ccflags-$(CONFIG_USB_DWC2_DEBUG) += -DDEBUG
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ccflags-$(CONFIG_USB_DWC2_VERBOSE) += -DVERBOSE_DEBUG
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obj-$(CONFIG_USB_DWC2) += dwc2.o
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dwc2-y += core.o core_intr.o
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# NOTE: This driver at present only implements the Host mode
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# of the controller. The existing s3c-hsotg driver supports
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# Peripheral mode, but only for the Samsung S3C platforms.
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# There are plans to merge the s3c-hsotg driver with this
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# driver in the near future to create a dual-role driver. Once
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# that is done, Host mode will become an optional feature that
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# is selected with a config option.
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obj-$(CONFIG_USB_DWC2_HOST) += dwc2.o
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dwc2-y := core.o core_intr.o
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dwc2-y += hcd.o hcd_intr.o
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dwc2-y += hcd_queue.o hcd_ddma.o
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ifneq ($(CONFIG_PCI),)
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obj-$(CONFIG_USB_DWC2) += dwc2_pci.o
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endif
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obj-$(CONFIG_USB_DWC2) += dwc2_platform.o
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# NOTE: The previous s3c-hsotg peripheral mode only driver has been moved to
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# this location and renamed gadget.c. When building for dynamically linked
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# modules, dwc2_gadget.ko will get built for peripheral mode. For host mode,
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# the core module will be dwc2.ko, the PCI bus interface module will called
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# dwc2_pci.ko and the platform interface module will be called dwc2_platform.ko.
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# At present the host and gadget driver will be separate drivers, but there
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# are plans in the near future to create a dual-role driver.
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dwc2_pci-y += pci.o
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dwc2_platform-y += platform.o
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ifneq ($(CONFIG_USB_DWC2_PCI),)
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obj-$(CONFIG_USB_DWC2_HOST) += dwc2_pci.o
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dwc2_pci-y := pci.o
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endif
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ifneq ($(CONFIG_USB_DWC2_PLATFORM),)
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obj-$(CONFIG_USB_DWC2_HOST) += dwc2_platform.o
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dwc2_platform-y := platform.o
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endif
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obj-$(CONFIG_USB_DWC2_PERIPHERAL) += dwc2_gadget.o
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dwc2_gadget-y := gadget.o
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File diff suppressed because it is too large
Load diff
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@ -300,12 +300,6 @@ config USB_PXA27X
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dynamically linked module called "pxa27x_udc" and force all
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gadget drivers to also be dynamically linked.
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config USB_S3C_HSOTG
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tristate "Designware/S3C HS/OtG USB Device controller"
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help
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The Designware USB2.0 high-speed gadget controller
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integrated into many SoCs.
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config USB_S3C2410
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tristate "S3C2410 USB Device Controller"
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depends on ARCH_S3C24XX
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@ -26,7 +26,6 @@ fsl_usb2_udc-$(CONFIG_ARCH_MXC) += fsl_mxc_udc.o
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obj-$(CONFIG_USB_M66592) += m66592-udc.o
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obj-$(CONFIG_USB_R8A66597) += r8a66597-udc.o
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obj-$(CONFIG_USB_FSL_QE) += fsl_qe_udc.o
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obj-$(CONFIG_USB_S3C_HSOTG) += s3c-hsotg.o
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obj-$(CONFIG_USB_S3C_HSUDC) += s3c-hsudc.o
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obj-$(CONFIG_USB_LPC32XX) += lpc32xx_udc.o
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obj-$(CONFIG_USB_EG20T) += pch_udc.o
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@ -1,378 +0,0 @@
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/* drivers/usb/gadget/s3c-hsotg.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* USB2.0 Highspeed/OtG Synopsis DWC2 device block registers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __REGS_USB_HSOTG_H
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#define __REGS_USB_HSOTG_H __FILE__
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#define HSOTG_REG(x) (x)
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#define GOTGCTL HSOTG_REG(0x000)
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#define GOTGCTL_BSESVLD (1 << 19)
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#define GOTGCTL_ASESVLD (1 << 18)
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#define GOTGCTL_DBNC_SHORT (1 << 17)
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#define GOTGCTL_CONID_B (1 << 16)
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#define GOTGCTL_DEVHNPEN (1 << 11)
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#define GOTGCTL_HSSETHNPEN (1 << 10)
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#define GOTGCTL_HNPREQ (1 << 9)
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#define GOTGCTL_HSTNEGSCS (1 << 8)
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#define GOTGCTL_SESREQ (1 << 1)
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#define GOTGCTL_SESREQSCS (1 << 0)
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#define GOTGINT HSOTG_REG(0x004)
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#define GOTGINT_DbnceDone (1 << 19)
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#define GOTGINT_ADevTOUTChg (1 << 18)
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#define GOTGINT_HstNegDet (1 << 17)
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#define GOTGINT_HstnegSucStsChng (1 << 9)
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#define GOTGINT_SesReqSucStsChng (1 << 8)
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#define GOTGINT_SesEndDet (1 << 2)
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#define GAHBCFG HSOTG_REG(0x008)
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#define GAHBCFG_PTxFEmpLvl (1 << 8)
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#define GAHBCFG_NPTxFEmpLvl (1 << 7)
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#define GAHBCFG_DMAEn (1 << 5)
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#define GAHBCFG_HBstLen_MASK (0xf << 1)
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#define GAHBCFG_HBstLen_SHIFT (1)
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#define GAHBCFG_HBstLen_Single (0x0 << 1)
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#define GAHBCFG_HBstLen_Incr (0x1 << 1)
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#define GAHBCFG_HBstLen_Incr4 (0x3 << 1)
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#define GAHBCFG_HBstLen_Incr8 (0x5 << 1)
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#define GAHBCFG_HBstLen_Incr16 (0x7 << 1)
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#define GAHBCFG_GlblIntrEn (1 << 0)
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#define GUSBCFG HSOTG_REG(0x00C)
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#define GUSBCFG_PHYLPClkSel (1 << 15)
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#define GUSBCFG_HNPCap (1 << 9)
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#define GUSBCFG_SRPCap (1 << 8)
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#define GUSBCFG_PHYIf16 (1 << 3)
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#define GUSBCFG_PHYIf8 (0 << 3)
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#define GUSBCFG_TOutCal_MASK (0x7 << 0)
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#define GUSBCFG_TOutCal_SHIFT (0)
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#define GUSBCFG_TOutCal_LIMIT (0x7)
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#define GUSBCFG_TOutCal(_x) ((_x) << 0)
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#define GRSTCTL HSOTG_REG(0x010)
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#define GRSTCTL_AHBIdle (1 << 31)
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#define GRSTCTL_DMAReq (1 << 30)
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#define GRSTCTL_TxFNum_MASK (0x1f << 6)
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#define GRSTCTL_TxFNum_SHIFT (6)
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#define GRSTCTL_TxFNum_LIMIT (0x1f)
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#define GRSTCTL_TxFNum(_x) ((_x) << 6)
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#define GRSTCTL_TxFFlsh (1 << 5)
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#define GRSTCTL_RxFFlsh (1 << 4)
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#define GRSTCTL_INTknQFlsh (1 << 3)
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#define GRSTCTL_FrmCntrRst (1 << 2)
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#define GRSTCTL_HSftRst (1 << 1)
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#define GRSTCTL_CSftRst (1 << 0)
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#define GINTSTS HSOTG_REG(0x014)
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#define GINTMSK HSOTG_REG(0x018)
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#define GINTSTS_WkUpInt (1 << 31)
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#define GINTSTS_SessReqInt (1 << 30)
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#define GINTSTS_DisconnInt (1 << 29)
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#define GINTSTS_ConIDStsChng (1 << 28)
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#define GINTSTS_PTxFEmp (1 << 26)
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#define GINTSTS_HChInt (1 << 25)
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#define GINTSTS_PrtInt (1 << 24)
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#define GINTSTS_FetSusp (1 << 22)
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#define GINTSTS_incompIP (1 << 21)
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#define GINTSTS_IncomplSOIN (1 << 20)
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#define GINTSTS_OEPInt (1 << 19)
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#define GINTSTS_IEPInt (1 << 18)
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#define GINTSTS_EPMis (1 << 17)
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#define GINTSTS_EOPF (1 << 15)
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#define GINTSTS_ISOutDrop (1 << 14)
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#define GINTSTS_EnumDone (1 << 13)
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#define GINTSTS_USBRst (1 << 12)
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#define GINTSTS_USBSusp (1 << 11)
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#define GINTSTS_ErlySusp (1 << 10)
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#define GINTSTS_GOUTNakEff (1 << 7)
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#define GINTSTS_GINNakEff (1 << 6)
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#define GINTSTS_NPTxFEmp (1 << 5)
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#define GINTSTS_RxFLvl (1 << 4)
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#define GINTSTS_SOF (1 << 3)
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#define GINTSTS_OTGInt (1 << 2)
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#define GINTSTS_ModeMis (1 << 1)
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#define GINTSTS_CurMod_Host (1 << 0)
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#define GRXSTSR HSOTG_REG(0x01C)
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#define GRXSTSP HSOTG_REG(0x020)
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#define GRXSTS_FN_MASK (0x7f << 25)
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#define GRXSTS_FN_SHIFT (25)
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#define GRXSTS_PktSts_MASK (0xf << 17)
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#define GRXSTS_PktSts_SHIFT (17)
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#define GRXSTS_PktSts_GlobalOutNAK (0x1 << 17)
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#define GRXSTS_PktSts_OutRX (0x2 << 17)
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#define GRXSTS_PktSts_OutDone (0x3 << 17)
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#define GRXSTS_PktSts_SetupDone (0x4 << 17)
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#define GRXSTS_PktSts_SetupRX (0x6 << 17)
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#define GRXSTS_DPID_MASK (0x3 << 15)
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#define GRXSTS_DPID_SHIFT (15)
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#define GRXSTS_ByteCnt_MASK (0x7ff << 4)
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#define GRXSTS_ByteCnt_SHIFT (4)
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#define GRXSTS_EPNum_MASK (0xf << 0)
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#define GRXSTS_EPNum_SHIFT (0)
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#define GRXFSIZ HSOTG_REG(0x024)
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#define GNPTXFSIZ HSOTG_REG(0x028)
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#define GNPTXFSIZ_NPTxFDep_MASK (0xffff << 16)
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#define GNPTXFSIZ_NPTxFDep_SHIFT (16)
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#define GNPTXFSIZ_NPTxFDep_LIMIT (0xffff)
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#define GNPTXFSIZ_NPTxFDep(_x) ((_x) << 16)
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#define GNPTXFSIZ_NPTxFStAddr_MASK (0xffff << 0)
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#define GNPTXFSIZ_NPTxFStAddr_SHIFT (0)
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#define GNPTXFSIZ_NPTxFStAddr_LIMIT (0xffff)
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#define GNPTXFSIZ_NPTxFStAddr(_x) ((_x) << 0)
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#define GNPTXSTS HSOTG_REG(0x02C)
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#define GNPTXSTS_NPtxQTop_MASK (0x7f << 24)
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#define GNPTXSTS_NPtxQTop_SHIFT (24)
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#define GNPTXSTS_NPTxQSpcAvail_MASK (0xff << 16)
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#define GNPTXSTS_NPTxQSpcAvail_SHIFT (16)
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#define GNPTXSTS_NPTxQSpcAvail_GET(_v) (((_v) >> 16) & 0xff)
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#define GNPTXSTS_NPTxFSpcAvail_MASK (0xffff << 0)
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#define GNPTXSTS_NPTxFSpcAvail_SHIFT (0)
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#define GNPTXSTS_NPTxFSpcAvail_GET(_v) (((_v) >> 0) & 0xffff)
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#define HPTXFSIZ HSOTG_REG(0x100)
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#define DPTXFSIZn(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4))
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#define DPTXFSIZn_DPTxFSize_MASK (0xffff << 16)
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#define DPTXFSIZn_DPTxFSize_SHIFT (16)
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#define DPTXFSIZn_DPTxFSize_GET(_v) (((_v) >> 16) & 0xffff)
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#define DPTXFSIZn_DPTxFSize_LIMIT (0xffff)
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#define DPTXFSIZn_DPTxFSize(_x) ((_x) << 16)
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#define DPTXFSIZn_DPTxFStAddr_MASK (0xffff << 0)
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#define DPTXFSIZn_DPTxFStAddr_SHIFT (0)
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/* Device mode registers */
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#define DCFG HSOTG_REG(0x800)
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#define DCFG_EPMisCnt_MASK (0x1f << 18)
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#define DCFG_EPMisCnt_SHIFT (18)
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#define DCFG_EPMisCnt_LIMIT (0x1f)
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#define DCFG_EPMisCnt(_x) ((_x) << 18)
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#define DCFG_PerFrInt_MASK (0x3 << 11)
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#define DCFG_PerFrInt_SHIFT (11)
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#define DCFG_PerFrInt_LIMIT (0x3)
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#define DCFG_PerFrInt(_x) ((_x) << 11)
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#define DCFG_DevAddr_MASK (0x7f << 4)
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#define DCFG_DevAddr_SHIFT (4)
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#define DCFG_DevAddr_LIMIT (0x7f)
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#define DCFG_DevAddr(_x) ((_x) << 4)
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#define DCFG_NZStsOUTHShk (1 << 2)
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#define DCFG_DevSpd_MASK (0x3 << 0)
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#define DCFG_DevSpd_SHIFT (0)
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#define DCFG_DevSpd_HS (0x0 << 0)
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#define DCFG_DevSpd_FS (0x1 << 0)
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#define DCFG_DevSpd_LS (0x2 << 0)
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#define DCFG_DevSpd_FS48 (0x3 << 0)
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#define DCTL HSOTG_REG(0x804)
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#define DCTL_PWROnPrgDone (1 << 11)
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#define DCTL_CGOUTNak (1 << 10)
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#define DCTL_SGOUTNak (1 << 9)
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#define DCTL_CGNPInNAK (1 << 8)
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#define DCTL_SGNPInNAK (1 << 7)
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#define DCTL_TstCtl_MASK (0x7 << 4)
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#define DCTL_TstCtl_SHIFT (4)
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#define DCTL_GOUTNakSts (1 << 3)
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#define DCTL_GNPINNakSts (1 << 2)
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#define DCTL_SftDiscon (1 << 1)
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#define DCTL_RmtWkUpSig (1 << 0)
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#define DSTS HSOTG_REG(0x808)
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#define DSTS_SOFFN_MASK (0x3fff << 8)
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#define DSTS_SOFFN_SHIFT (8)
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#define DSTS_SOFFN_LIMIT (0x3fff)
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#define DSTS_SOFFN(_x) ((_x) << 8)
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#define DSTS_ErraticErr (1 << 3)
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#define DSTS_EnumSpd_MASK (0x3 << 1)
|
||||
#define DSTS_EnumSpd_SHIFT (1)
|
||||
#define DSTS_EnumSpd_HS (0x0 << 1)
|
||||
#define DSTS_EnumSpd_FS (0x1 << 1)
|
||||
#define DSTS_EnumSpd_LS (0x2 << 1)
|
||||
#define DSTS_EnumSpd_FS48 (0x3 << 1)
|
||||
|
||||
#define DSTS_SuspSts (1 << 0)
|
||||
|
||||
#define DIEPMSK HSOTG_REG(0x810)
|
||||
|
||||
#define DIEPMSK_TxFIFOEmpty (1 << 7)
|
||||
#define DIEPMSK_INEPNakEffMsk (1 << 6)
|
||||
#define DIEPMSK_INTknEPMisMsk (1 << 5)
|
||||
#define DIEPMSK_INTknTXFEmpMsk (1 << 4)
|
||||
#define DIEPMSK_TimeOUTMsk (1 << 3)
|
||||
#define DIEPMSK_AHBErrMsk (1 << 2)
|
||||
#define DIEPMSK_EPDisbldMsk (1 << 1)
|
||||
#define DIEPMSK_XferComplMsk (1 << 0)
|
||||
|
||||
#define DOEPMSK HSOTG_REG(0x814)
|
||||
|
||||
#define DOEPMSK_Back2BackSetup (1 << 6)
|
||||
#define DOEPMSK_OUTTknEPdisMsk (1 << 4)
|
||||
#define DOEPMSK_SetupMsk (1 << 3)
|
||||
#define DOEPMSK_AHBErrMsk (1 << 2)
|
||||
#define DOEPMSK_EPDisbldMsk (1 << 1)
|
||||
#define DOEPMSK_XferComplMsk (1 << 0)
|
||||
|
||||
#define DAINT HSOTG_REG(0x818)
|
||||
#define DAINTMSK HSOTG_REG(0x81C)
|
||||
|
||||
#define DAINT_OutEP_SHIFT (16)
|
||||
#define DAINT_OutEP(x) (1 << ((x) + 16))
|
||||
#define DAINT_InEP(x) (1 << (x))
|
||||
|
||||
#define DTKNQR1 HSOTG_REG(0x820)
|
||||
#define DTKNQR2 HSOTG_REG(0x824)
|
||||
#define DTKNQR3 HSOTG_REG(0x830)
|
||||
#define DTKNQR4 HSOTG_REG(0x834)
|
||||
|
||||
#define DVBUSDIS HSOTG_REG(0x828)
|
||||
#define DVBUSPULSE HSOTG_REG(0x82C)
|
||||
|
||||
#define DIEPCTL0 HSOTG_REG(0x900)
|
||||
#define DOEPCTL0 HSOTG_REG(0xB00)
|
||||
#define DIEPCTL(_a) HSOTG_REG(0x900 + ((_a) * 0x20))
|
||||
#define DOEPCTL(_a) HSOTG_REG(0xB00 + ((_a) * 0x20))
|
||||
|
||||
/* EP0 specialness:
|
||||
* bits[29..28] - reserved (no SetD0PID, SetD1PID)
|
||||
* bits[25..22] - should always be zero, this isn't a periodic endpoint
|
||||
* bits[10..0] - MPS setting differenct for EP0
|
||||
*/
|
||||
#define D0EPCTL_MPS_MASK (0x3 << 0)
|
||||
#define D0EPCTL_MPS_SHIFT (0)
|
||||
#define D0EPCTL_MPS_64 (0x0 << 0)
|
||||
#define D0EPCTL_MPS_32 (0x1 << 0)
|
||||
#define D0EPCTL_MPS_16 (0x2 << 0)
|
||||
#define D0EPCTL_MPS_8 (0x3 << 0)
|
||||
|
||||
#define DxEPCTL_EPEna (1 << 31)
|
||||
#define DxEPCTL_EPDis (1 << 30)
|
||||
#define DxEPCTL_SetD1PID (1 << 29)
|
||||
#define DxEPCTL_SetOddFr (1 << 29)
|
||||
#define DxEPCTL_SetD0PID (1 << 28)
|
||||
#define DxEPCTL_SetEvenFr (1 << 28)
|
||||
#define DxEPCTL_SNAK (1 << 27)
|
||||
#define DxEPCTL_CNAK (1 << 26)
|
||||
#define DxEPCTL_TxFNum_MASK (0xf << 22)
|
||||
#define DxEPCTL_TxFNum_SHIFT (22)
|
||||
#define DxEPCTL_TxFNum_LIMIT (0xf)
|
||||
#define DxEPCTL_TxFNum(_x) ((_x) << 22)
|
||||
|
||||
#define DxEPCTL_Stall (1 << 21)
|
||||
#define DxEPCTL_Snp (1 << 20)
|
||||
#define DxEPCTL_EPType_MASK (0x3 << 18)
|
||||
#define DxEPCTL_EPType_SHIFT (18)
|
||||
#define DxEPCTL_EPType_Control (0x0 << 18)
|
||||
#define DxEPCTL_EPType_Iso (0x1 << 18)
|
||||
#define DxEPCTL_EPType_Bulk (0x2 << 18)
|
||||
#define DxEPCTL_EPType_Intterupt (0x3 << 18)
|
||||
|
||||
#define DxEPCTL_NAKsts (1 << 17)
|
||||
#define DxEPCTL_DPID (1 << 16)
|
||||
#define DxEPCTL_EOFrNum (1 << 16)
|
||||
#define DxEPCTL_USBActEp (1 << 15)
|
||||
#define DxEPCTL_NextEp_MASK (0xf << 11)
|
||||
#define DxEPCTL_NextEp_SHIFT (11)
|
||||
#define DxEPCTL_NextEp_LIMIT (0xf)
|
||||
#define DxEPCTL_NextEp(_x) ((_x) << 11)
|
||||
|
||||
#define DxEPCTL_MPS_MASK (0x7ff << 0)
|
||||
#define DxEPCTL_MPS_SHIFT (0)
|
||||
#define DxEPCTL_MPS_LIMIT (0x7ff)
|
||||
#define DxEPCTL_MPS(_x) ((_x) << 0)
|
||||
|
||||
#define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20))
|
||||
#define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20))
|
||||
|
||||
#define DxEPINT_INEPNakEff (1 << 6)
|
||||
#define DxEPINT_Back2BackSetup (1 << 6)
|
||||
#define DxEPINT_INTknEPMis (1 << 5)
|
||||
#define DxEPINT_INTknTXFEmp (1 << 4)
|
||||
#define DxEPINT_OUTTknEPdis (1 << 4)
|
||||
#define DxEPINT_Timeout (1 << 3)
|
||||
#define DxEPINT_Setup (1 << 3)
|
||||
#define DxEPINT_AHBErr (1 << 2)
|
||||
#define DxEPINT_EPDisbld (1 << 1)
|
||||
#define DxEPINT_XferCompl (1 << 0)
|
||||
|
||||
#define DIEPTSIZ0 HSOTG_REG(0x910)
|
||||
|
||||
#define DIEPTSIZ0_PktCnt_MASK (0x3 << 19)
|
||||
#define DIEPTSIZ0_PktCnt_SHIFT (19)
|
||||
#define DIEPTSIZ0_PktCnt_LIMIT (0x3)
|
||||
#define DIEPTSIZ0_PktCnt(_x) ((_x) << 19)
|
||||
|
||||
#define DIEPTSIZ0_XferSize_MASK (0x7f << 0)
|
||||
#define DIEPTSIZ0_XferSize_SHIFT (0)
|
||||
#define DIEPTSIZ0_XferSize_LIMIT (0x7f)
|
||||
#define DIEPTSIZ0_XferSize(_x) ((_x) << 0)
|
||||
|
||||
#define DOEPTSIZ0 HSOTG_REG(0xB10)
|
||||
#define DOEPTSIZ0_SUPCnt_MASK (0x3 << 29)
|
||||
#define DOEPTSIZ0_SUPCnt_SHIFT (29)
|
||||
#define DOEPTSIZ0_SUPCnt_LIMIT (0x3)
|
||||
#define DOEPTSIZ0_SUPCnt(_x) ((_x) << 29)
|
||||
|
||||
#define DOEPTSIZ0_PktCnt (1 << 19)
|
||||
#define DOEPTSIZ0_XferSize_MASK (0x7f << 0)
|
||||
#define DOEPTSIZ0_XferSize_SHIFT (0)
|
||||
|
||||
#define DIEPTSIZ(_a) HSOTG_REG(0x910 + ((_a) * 0x20))
|
||||
#define DOEPTSIZ(_a) HSOTG_REG(0xB10 + ((_a) * 0x20))
|
||||
|
||||
#define DxEPTSIZ_MC_MASK (0x3 << 29)
|
||||
#define DxEPTSIZ_MC_SHIFT (29)
|
||||
#define DxEPTSIZ_MC_LIMIT (0x3)
|
||||
#define DxEPTSIZ_MC(_x) ((_x) << 29)
|
||||
|
||||
#define DxEPTSIZ_PktCnt_MASK (0x3ff << 19)
|
||||
#define DxEPTSIZ_PktCnt_SHIFT (19)
|
||||
#define DxEPTSIZ_PktCnt_GET(_v) (((_v) >> 19) & 0x3ff)
|
||||
#define DxEPTSIZ_PktCnt_LIMIT (0x3ff)
|
||||
#define DxEPTSIZ_PktCnt(_x) ((_x) << 19)
|
||||
|
||||
#define DxEPTSIZ_XferSize_MASK (0x7ffff << 0)
|
||||
#define DxEPTSIZ_XferSize_SHIFT (0)
|
||||
#define DxEPTSIZ_XferSize_GET(_v) (((_v) >> 0) & 0x7ffff)
|
||||
#define DxEPTSIZ_XferSize_LIMIT (0x7ffff)
|
||||
#define DxEPTSIZ_XferSize(_x) ((_x) << 0)
|
||||
|
||||
#define DIEPDMA(_a) HSOTG_REG(0x914 + ((_a) * 0x20))
|
||||
#define DOEPDMA(_a) HSOTG_REG(0xB14 + ((_a) * 0x20))
|
||||
#define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20))
|
||||
|
||||
#define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000))
|
||||
|
||||
#endif /* __REGS_USB_HSOTG_H */
|
||||
Loading…
Reference in a new issue