x86: perfctr-watchdog.c - coding style cleanup
Just some code beautification. Nothing else. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com> Cc: macro@linux-mips.org Signed-off-by: Ingo Molnar <mingo@elte.hu>hifive-unleashed-5.1
Cyrill Gorcunov
Ingo Molnar
parent
2bc0d2615a
commit
47a486cc11
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@ -1,11 +1,15 @@
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/* local apic based NMI watchdog for various CPUs.
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This file also handles reservation of performance counters for coordination
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with other users (like oprofile).
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Note that these events normally don't tick when the CPU idles. This means
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the frequency varies with CPU load.
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Original code for K7/P6 written by Keith Owens */
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/*
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* local apic based NMI watchdog for various CPUs.
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*
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* This file also handles reservation of performance counters for coordination
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* with other users (like oprofile).
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*
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* Note that these events normally don't tick when the CPU idles. This means
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* the frequency varies with CPU load.
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*
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* Original code for K7/P6 written by Keith Owens
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*
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*/
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#include <linux/percpu.h>
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#include <linux/module.h>
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@ -36,12 +40,16 @@ struct wd_ops {
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static const struct wd_ops *wd_ops;
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/* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
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* offset from MSR_P4_BSU_ESCR0. It will be the max for all platforms (for now)
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/*
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* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
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* offset from MSR_P4_BSU_ESCR0.
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*
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* It will be the max for all platforms (for now)
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*/
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#define NMI_MAX_COUNTER_BITS 66
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/* perfctr_nmi_owner tracks the ownership of the perfctr registers:
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/*
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* perfctr_nmi_owner tracks the ownership of the perfctr registers:
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* evtsel_nmi_owner tracks the ownership of the event selection
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* - different performance counters/ event selection may be reserved for
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* different subsystems this reservation system just tries to coordinate
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@ -73,8 +81,10 @@ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
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return 0;
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}
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/* converts an msr to an appropriate reservation bit */
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/* returns the bit offset of the event selection register */
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/*
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* converts an msr to an appropriate reservation bit
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* returns the bit offset of the event selection register
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*/
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static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
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{
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/* returns the bit offset of the event selection register */
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@ -114,6 +124,7 @@ int avail_to_resrv_perfctr_nmi(unsigned int msr)
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return (!test_bit(counter, perfctr_nmi_owner));
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}
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EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
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int reserve_perfctr_nmi(unsigned int msr)
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{
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@ -128,6 +139,7 @@ int reserve_perfctr_nmi(unsigned int msr)
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return 1;
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return 0;
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}
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EXPORT_SYMBOL(reserve_perfctr_nmi);
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void release_perfctr_nmi(unsigned int msr)
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{
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@ -140,6 +152,7 @@ void release_perfctr_nmi(unsigned int msr)
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clear_bit(counter, perfctr_nmi_owner);
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}
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EXPORT_SYMBOL(release_perfctr_nmi);
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int reserve_evntsel_nmi(unsigned int msr)
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{
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@ -154,6 +167,7 @@ int reserve_evntsel_nmi(unsigned int msr)
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return 1;
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return 0;
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}
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EXPORT_SYMBOL(reserve_evntsel_nmi);
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void release_evntsel_nmi(unsigned int msr)
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{
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@ -166,11 +180,6 @@ void release_evntsel_nmi(unsigned int msr)
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clear_bit(counter, evntsel_nmi_owner);
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}
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EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
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EXPORT_SYMBOL(reserve_perfctr_nmi);
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EXPORT_SYMBOL(release_perfctr_nmi);
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EXPORT_SYMBOL(reserve_evntsel_nmi);
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EXPORT_SYMBOL(release_evntsel_nmi);
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void disable_lapic_nmi_watchdog(void)
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@ -234,8 +243,8 @@ static unsigned int adjust_for_32bit_ctr(unsigned int hz)
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return retval;
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}
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static void
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write_watchdog_counter(unsigned int perfctr_msr, const char *descr, unsigned nmi_hz)
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static void write_watchdog_counter(unsigned int perfctr_msr,
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const char *descr, unsigned nmi_hz)
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{
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u64 count = (u64)cpu_khz * 1000;
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@ -246,7 +255,7 @@ write_watchdog_counter(unsigned int perfctr_msr, const char *descr, unsigned nmi
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}
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static void write_watchdog_counter32(unsigned int perfctr_msr,
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const char *descr, unsigned nmi_hz)
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const char *descr, unsigned nmi_hz)
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{
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u64 count = (u64)cpu_khz * 1000;
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@ -256,9 +265,10 @@ static void write_watchdog_counter32(unsigned int perfctr_msr,
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wrmsr(perfctr_msr, (u32)(-count), 0);
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}
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/* AMD K7/K8/Family10h/Family11h support. AMD keeps this interface
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nicely stable so there is not much variety */
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/*
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* AMD K7/K8/Family10h/Family11h support.
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* AMD keeps this interface nicely stable so there is not much variety
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*/
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#define K7_EVNTSEL_ENABLE (1 << 22)
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#define K7_EVNTSEL_INT (1 << 20)
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#define K7_EVNTSEL_OS (1 << 17)
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@ -291,7 +301,7 @@ static int setup_k7_watchdog(unsigned nmi_hz)
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wd->perfctr_msr = perfctr_msr;
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wd->evntsel_msr = evntsel_msr;
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wd->cccr_msr = 0; //unused
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wd->cccr_msr = 0; /* unused */
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return 1;
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}
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@ -327,18 +337,19 @@ static void single_msr_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
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}
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static const struct wd_ops k7_wd_ops = {
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.reserve = single_msr_reserve,
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.unreserve = single_msr_unreserve,
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.setup = setup_k7_watchdog,
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.rearm = single_msr_rearm,
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.stop = single_msr_stop_watchdog,
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.perfctr = MSR_K7_PERFCTR0,
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.evntsel = MSR_K7_EVNTSEL0,
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.checkbit = 1ULL<<47,
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.reserve = single_msr_reserve,
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.unreserve = single_msr_unreserve,
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.setup = setup_k7_watchdog,
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.rearm = single_msr_rearm,
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.stop = single_msr_stop_watchdog,
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.perfctr = MSR_K7_PERFCTR0,
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.evntsel = MSR_K7_EVNTSEL0,
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.checkbit = 1ULL << 47,
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};
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/* Intel Model 6 (PPro+,P2,P3,P-M,Core1) */
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/*
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* Intel Model 6 (PPro+,P2,P3,P-M,Core1)
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*/
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#define P6_EVNTSEL0_ENABLE (1 << 22)
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#define P6_EVNTSEL_INT (1 << 20)
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#define P6_EVNTSEL_OS (1 << 17)
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@ -374,52 +385,58 @@ static int setup_p6_watchdog(unsigned nmi_hz)
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wd->perfctr_msr = perfctr_msr;
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wd->evntsel_msr = evntsel_msr;
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wd->cccr_msr = 0; //unused
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wd->cccr_msr = 0; /* unused */
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return 1;
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}
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static void p6_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
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{
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/* P6 based Pentium M need to re-unmask
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/*
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* P6 based Pentium M need to re-unmask
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* the apic vector but it doesn't hurt
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* other P6 variant.
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* ArchPerfom/Core Duo also needs this */
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* ArchPerfom/Core Duo also needs this
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*/
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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/* P6/ARCH_PERFMON has 32 bit counter write */
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write_watchdog_counter32(wd->perfctr_msr, NULL,nmi_hz);
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}
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static const struct wd_ops p6_wd_ops = {
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.reserve = single_msr_reserve,
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.unreserve = single_msr_unreserve,
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.setup = setup_p6_watchdog,
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.rearm = p6_rearm,
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.stop = single_msr_stop_watchdog,
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.perfctr = MSR_P6_PERFCTR0,
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.evntsel = MSR_P6_EVNTSEL0,
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.checkbit = 1ULL<<39,
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.reserve = single_msr_reserve,
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.unreserve = single_msr_unreserve,
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.setup = setup_p6_watchdog,
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.rearm = p6_rearm,
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.stop = single_msr_stop_watchdog,
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.perfctr = MSR_P6_PERFCTR0,
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.evntsel = MSR_P6_EVNTSEL0,
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.checkbit = 1ULL << 39,
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};
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/* Intel P4 performance counters. By far the most complicated of all. */
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#define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
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#define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
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#define P4_ESCR_OS (1<<3)
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#define P4_ESCR_USR (1<<2)
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#define P4_CCCR_OVF_PMI0 (1<<26)
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#define P4_CCCR_OVF_PMI1 (1<<27)
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#define P4_CCCR_THRESHOLD(N) ((N)<<20)
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#define P4_CCCR_COMPLEMENT (1<<19)
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#define P4_CCCR_COMPARE (1<<18)
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#define P4_CCCR_REQUIRED (3<<16)
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#define P4_CCCR_ESCR_SELECT(N) ((N)<<13)
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#define P4_CCCR_ENABLE (1<<12)
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#define P4_CCCR_OVF (1<<31)
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/* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
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CRU_ESCR0 (with any non-null event selector) through a complemented
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max threshold. [IA32-Vol3, Section 14.9.9] */
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/*
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* Intel P4 performance counters.
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* By far the most complicated of all.
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*/
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#define MSR_P4_MISC_ENABLE_PERF_AVAIL (1 << 7)
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#define P4_ESCR_EVENT_SELECT(N) ((N) << 25)
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#define P4_ESCR_OS (1 << 3)
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#define P4_ESCR_USR (1 << 2)
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#define P4_CCCR_OVF_PMI0 (1 << 26)
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#define P4_CCCR_OVF_PMI1 (1 << 27)
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#define P4_CCCR_THRESHOLD(N) ((N) << 20)
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#define P4_CCCR_COMPLEMENT (1 << 19)
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#define P4_CCCR_COMPARE (1 << 18)
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#define P4_CCCR_REQUIRED (3 << 16)
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#define P4_CCCR_ESCR_SELECT(N) ((N) << 13)
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#define P4_CCCR_ENABLE (1 << 12)
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#define P4_CCCR_OVF (1 << 31)
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/*
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* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
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* CRU_ESCR0 (with any non-null event selector) through a complemented
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* max threshold. [IA32-Vol3, Section 14.9.9]
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*/
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static int setup_p4_watchdog(unsigned nmi_hz)
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{
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unsigned int perfctr_msr, evntsel_msr, cccr_msr;
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@ -444,7 +461,8 @@ static int setup_p4_watchdog(unsigned nmi_hz)
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#endif
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ht_num = 0;
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/* performance counters are shared resources
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/*
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* performance counters are shared resources
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* assign each hyperthread its own set
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* (re-use the ESCR0 register, seems safe
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* and keeps the cccr_val the same)
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@ -542,20 +560,21 @@ static void p4_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
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}
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static const struct wd_ops p4_wd_ops = {
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.reserve = p4_reserve,
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.unreserve = p4_unreserve,
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.setup = setup_p4_watchdog,
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.rearm = p4_rearm,
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.stop = stop_p4_watchdog,
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.reserve = p4_reserve,
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.unreserve = p4_unreserve,
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.setup = setup_p4_watchdog,
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.rearm = p4_rearm,
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.stop = stop_p4_watchdog,
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/* RED-PEN this is wrong for the other sibling */
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.perfctr = MSR_P4_BPU_PERFCTR0,
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.evntsel = MSR_P4_BSU_ESCR0,
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.checkbit = 1ULL<<39,
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.perfctr = MSR_P4_BPU_PERFCTR0,
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.evntsel = MSR_P4_BSU_ESCR0,
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.checkbit = 1ULL << 39,
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};
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/* Watchdog using the Intel architected PerfMon. Used for Core2 and hopefully
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all future Intel CPUs. */
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/*
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* Watchdog using the Intel architected PerfMon.
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* Used for Core2 and hopefully all future Intel CPUs.
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*/
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#define ARCH_PERFMON_NMI_EVENT_SEL ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
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#define ARCH_PERFMON_NMI_EVENT_UMASK ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
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@ -601,19 +620,19 @@ static int setup_intel_arch_watchdog(unsigned nmi_hz)
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wd->perfctr_msr = perfctr_msr;
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wd->evntsel_msr = evntsel_msr;
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wd->cccr_msr = 0; //unused
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wd->cccr_msr = 0; /* unused */
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intel_arch_wd_ops.checkbit = 1ULL << (eax.split.bit_width - 1);
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return 1;
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}
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static struct wd_ops intel_arch_wd_ops __read_mostly = {
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.reserve = single_msr_reserve,
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.unreserve = single_msr_unreserve,
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.setup = setup_intel_arch_watchdog,
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.rearm = p6_rearm,
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.stop = single_msr_stop_watchdog,
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.perfctr = MSR_ARCH_PERFMON_PERFCTR1,
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.evntsel = MSR_ARCH_PERFMON_EVENTSEL1,
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.reserve = single_msr_reserve,
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.unreserve = single_msr_unreserve,
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.setup = setup_intel_arch_watchdog,
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.rearm = p6_rearm,
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.stop = single_msr_stop_watchdog,
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.perfctr = MSR_ARCH_PERFMON_PERFCTR1,
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.evntsel = MSR_ARCH_PERFMON_EVENTSEL1,
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};
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static void probe_nmi_watchdog(void)
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@ -626,8 +645,10 @@ static void probe_nmi_watchdog(void)
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wd_ops = &k7_wd_ops;
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break;
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case X86_VENDOR_INTEL:
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/* Work around Core Duo (Yonah) errata AE49 where perfctr1
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doesn't have a working enable bit. */
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/*
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* Work around Core Duo (Yonah) errata AE49 where perfctr1
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* doesn't have a working enable bit.
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*/
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if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 14) {
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intel_arch_wd_ops.perfctr = MSR_ARCH_PERFMON_PERFCTR0;
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intel_arch_wd_ops.evntsel = MSR_ARCH_PERFMON_EVENTSEL0;
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@ -638,7 +659,7 @@ static void probe_nmi_watchdog(void)
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}
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switch (boot_cpu_data.x86) {
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case 6:
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if (boot_cpu_data.x86_model > 0xd)
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if (boot_cpu_data.x86_model > 13)
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return;
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wd_ops = &p6_wd_ops;
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@ -699,10 +720,11 @@ int lapic_wd_event(unsigned nmi_hz)
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{
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struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
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u64 ctr;
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rdmsrl(wd->perfctr_msr, ctr);
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if (ctr & wd_ops->checkbit) { /* perfctr still running? */
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if (ctr & wd_ops->checkbit) /* perfctr still running? */
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return 0;
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}
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wd_ops->rearm(wd, nmi_hz);
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return 1;
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}
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