[media] s5h1432: Add new s5h1432 driver
Introduce a new driver for the s5h1432 Signed-off-by: Palash Bandyopadhyay <palash.bandyopadhyay@conexant.com> Signed-off-by: Devin Heitmueller <dheitmueller@hauppauge.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Palash Bandyopadhyay
Mauro Carvalho Chehab
parent
e4115bb284
commit
47b75ec146
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@ -257,6 +257,13 @@ config DVB_CX22702
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help
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A DVB-T tuner module. Say Y when you want to support this frontend.
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config DVB_S5H1432
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tristate "Samsung s5h1432 demodulator (OFDM)"
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depends on DVB_CORE && I2C
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default m if DVB_FE_CUSTOMISE
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help
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A DVB-T tuner module. Say Y when you want to support this frontend.
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config DVB_DRX397XD
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tristate "Micronas DRX3975D/DRX3977D based"
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depends on DVB_CORE && I2C
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@ -16,6 +16,7 @@ obj-$(CONFIG_DVB_STB0899) += stb0899.o
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obj-$(CONFIG_DVB_STB6100) += stb6100.o
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obj-$(CONFIG_DVB_SP8870) += sp8870.o
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obj-$(CONFIG_DVB_CX22700) += cx22700.o
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obj-$(CONFIG_DVB_S5H1432) += s5h1432.o
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obj-$(CONFIG_DVB_CX24110) += cx24110.o
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obj-$(CONFIG_DVB_TDA8083) += tda8083.o
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obj-$(CONFIG_DVB_L64781) += l64781.o
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440
drivers/media/dvb/frontends/s5h1432.c
Normal file
440
drivers/media/dvb/frontends/s5h1432.c
Normal file
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@ -0,0 +1,440 @@
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/*
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Samsung s5h1432 DVB-T demodulator driver
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Copyright (C) 2009 Bill Liu <Bill.Liu@Conexant.com>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include "dvb_frontend.h"
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#include "s5h1432.h"
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struct s5h1432_state {
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struct i2c_adapter *i2c;
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/* configuration settings */
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const struct s5h1432_config *config;
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struct dvb_frontend frontend;
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fe_modulation_t current_modulation;
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unsigned int first_tune:1;
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u32 current_frequency;
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int if_freq;
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u8 inversion;
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};
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static int debug;
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#define dprintk(arg...) do { \
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if (debug) \
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printk(arg); \
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} while (0)
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static int s5h1432_writereg(struct s5h1432_state *state,
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u8 addr, u8 reg, u8 data)
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{
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int ret;
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u8 buf[] = { reg, data };
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struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = 2 };
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ret = i2c_transfer(state->i2c, &msg, 1);
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if (ret != 1)
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printk(KERN_ERR "%s: writereg error 0x%02x 0x%02x 0x%04x, "
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"ret == %i)\n", __func__, addr, reg, data, ret);
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return (ret != 1) ? -1 : 0;
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}
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static u8 s5h1432_readreg(struct s5h1432_state *state, u8 addr, u8 reg)
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{
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int ret;
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u8 b0[] = { reg };
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u8 b1[] = { 0 };
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struct i2c_msg msg[] = {
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{ .addr = addr, .flags = 0, .buf = b0, .len = 1 },
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{ .addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
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ret = i2c_transfer(state->i2c, msg, 2);
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if (ret != 2)
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printk(KERN_ERR "%s: readreg error (ret == %i)\n",
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__func__, ret);
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return b1[0];
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}
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static int s5h1432_sleep(struct dvb_frontend *fe)
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{
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return 0;
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}
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static int s5h1432_set_channel_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
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{
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struct s5h1432_state *state = fe->demodulator_priv;
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u8 reg = 0;
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/* Register [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2*/
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reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x2E);
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reg &= ~(0x0C);
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switch (bandwidth) {
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case 6:
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reg |= 0x08;
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break;
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case 7:
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reg |= 0x04;
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break;
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case 8:
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reg |= 0x00;
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break;
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default:
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return 0;
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}
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2E, reg);
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return 1;
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}
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static int s5h1432_set_IF(struct dvb_frontend *fe, u32 ifFreqHz)
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{
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struct s5h1432_state *state = fe->demodulator_priv;
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switch (ifFreqHz) {
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case TAIWAN_HI_IF_FREQ_44_MHZ:
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{
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x55);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x55);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0x15);
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break;
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}
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case EUROPE_HI_IF_FREQ_36_MHZ:
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{
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x00);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x00);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0x40);
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break;
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}
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case IF_FREQ_6_MHZ:
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{
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x00);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x00);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xe0);
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break;
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}
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case IF_FREQ_3point3_MHZ:
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{
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x66);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x66);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xEE);
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break;
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}
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case IF_FREQ_3point5_MHZ:
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{
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x55);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x55);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xED);
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break;
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}
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case IF_FREQ_4_MHZ:
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{
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0xAA);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0xAA);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xEA);
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break;
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}
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default:
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{
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u32 value = 0;
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value = (u32) (((48000 - (ifFreqHz / 1000)) * 512 *
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(u32) 32768) / (48 * 1000));
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printk(KERN_INFO "Default IFFreq %d :reg value = 0x%x \n",
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ifFreqHz, value);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 ,
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(u8) value & 0xFF);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 ,
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(u8)(value>>8) & 0xFF);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 ,
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(u8)(value>>16) & 0xFF);
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break;
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}
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}
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return 1;
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}
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/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
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static int s5h1432_set_frontend(struct dvb_frontend *fe,
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struct dvb_frontend_parameters *p)
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{
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u32 dvb_bandwidth = 8;
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struct s5h1432_state *state = fe->demodulator_priv;
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if (p->frequency == state->current_frequency) {
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/*current_frequency = p->frequency;*/
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/*state->current_frequency = p->frequency;*/
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} else {
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fe->ops.tuner_ops.set_params(fe, p); msleep(300);
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s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
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switch (p->u.ofdm.bandwidth) {
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case BANDWIDTH_6_MHZ:
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dvb_bandwidth = 6;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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case BANDWIDTH_7_MHZ:
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dvb_bandwidth = 7;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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case BANDWIDTH_8_MHZ:
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dvb_bandwidth = 8;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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default:
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return 0;
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}
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/*fe->ops.tuner_ops.set_params(fe, p);*/
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/*Soft Reset chip*/
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msleep(30);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
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msleep(30);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
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s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
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switch (p->u.ofdm.bandwidth) {
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case BANDWIDTH_6_MHZ:
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dvb_bandwidth = 6;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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case BANDWIDTH_7_MHZ:
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dvb_bandwidth = 7;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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case BANDWIDTH_8_MHZ:
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dvb_bandwidth = 8;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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default:
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return 0;
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}
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/*fe->ops.tuner_ops.set_params(fe,p);*/
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/*Soft Reset chip*/
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msleep(30);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
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msleep(30);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
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}
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state->current_frequency = p->frequency;
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return 0;
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}
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static int s5h1432_init(struct dvb_frontend *fe)
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{
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struct s5h1432_state *state = fe->demodulator_priv;
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u8 reg = 0;
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state->current_frequency = 0;
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printk(KERN_INFO " s5h1432_init().\n");
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/*Set VSB mode as default, this also does a soft reset*/
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/*Initialize registers*/
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x04, 0xa8);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x05, 0x01);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x07, 0x70);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x19, 0x80);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1b, 0x9D);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1c, 0x30);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1d, 0x20);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x1B);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2e, 0x40);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, 0x84);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x50, 0x5a);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x5a, 0xd3);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x68, 0x50);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xb8, 0x3c);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xc4, 0x10);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xcc, 0x9c);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xDA, 0x00);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe1, 0x94);
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/* s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf4, 0xa1);*/
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf9, 0x00);
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/*For NXP tuner*/
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/*Set 3.3MHz as default IF frequency*/
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x66);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x66);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xEE);
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/* Set reg 0x1E to get the full dynamic range */
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x31);
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/*Mode setting in demod*/
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reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x42);
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reg |= 0x80;
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, reg);
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/*Serial mode*/
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/*Soft Reset chip*/
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
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msleep(30);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
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return 0;
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}
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static int s5h1432_read_status(struct dvb_frontend *fe, fe_status_t *status)
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{
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return 0;
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}
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static int s5h1432_read_signal_strength(struct dvb_frontend *fe,
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u16 *signal_strength)
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{
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return 0;
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}
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static int s5h1432_read_snr(struct dvb_frontend *fe, u16 *snr)
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{
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return 0;
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}
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static int s5h1432_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
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{
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return 0;
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}
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static int s5h1432_read_ber(struct dvb_frontend *fe, u32 *ber)
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{
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return 0;
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}
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static int s5h1432_get_frontend(struct dvb_frontend *fe,
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struct dvb_frontend_parameters *p)
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{
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return 0;
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}
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static int s5h1432_get_tune_settings(struct dvb_frontend *fe,
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struct dvb_frontend_tune_settings *tune)
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{
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return 0;
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}
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static void s5h1432_release(struct dvb_frontend *fe)
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{
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struct s5h1432_state *state = fe->demodulator_priv;
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kfree(state);
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}
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static struct dvb_frontend_ops s5h1432_ops;
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struct dvb_frontend *s5h1432_attach(const struct s5h1432_config *config,
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struct i2c_adapter *i2c)
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{
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struct s5h1432_state *state = NULL;
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printk(KERN_INFO " Enter s5h1432_attach(). attach success!\n");
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/* allocate memory for the internal state */
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state = kmalloc(sizeof(struct s5h1432_state), GFP_KERNEL);
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if (state == NULL)
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goto error;
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/* setup the state */
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state->config = config;
|
||||
state->i2c = i2c;
|
||||
state->current_modulation = QAM_16;
|
||||
state->inversion = state->config->inversion;
|
||||
|
||||
/* create dvb_frontend */
|
||||
memcpy(&state->frontend.ops, &s5h1432_ops,
|
||||
sizeof(struct dvb_frontend_ops));
|
||||
|
||||
state->frontend.demodulator_priv = state;
|
||||
|
||||
return &state->frontend;
|
||||
|
||||
error:
|
||||
kfree(state);
|
||||
return NULL;
|
||||
}
|
||||
EXPORT_SYMBOL(s5h1432_attach);
|
||||
|
||||
static struct dvb_frontend_ops s5h1432_ops = {
|
||||
|
||||
.info = {
|
||||
.name = "Samsung s5h1432 DVB-T Frontend",
|
||||
.type = FE_OFDM,
|
||||
.frequency_min = 177000000,
|
||||
.frequency_max = 858000000,
|
||||
.frequency_stepsize = 166666,
|
||||
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
|
||||
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
|
||||
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
|
||||
FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
|
||||
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER
|
||||
},
|
||||
|
||||
.init = s5h1432_init,
|
||||
.sleep = s5h1432_sleep,
|
||||
.set_frontend = s5h1432_set_frontend,
|
||||
.get_frontend = s5h1432_get_frontend,
|
||||
.get_tune_settings = s5h1432_get_tune_settings,
|
||||
.read_status = s5h1432_read_status,
|
||||
.read_ber = s5h1432_read_ber,
|
||||
.read_signal_strength = s5h1432_read_signal_strength,
|
||||
.read_snr = s5h1432_read_snr,
|
||||
.read_ucblocks = s5h1432_read_ucblocks,
|
||||
.release = s5h1432_release,
|
||||
};
|
||||
|
||||
module_param(debug, int, 0644);
|
||||
MODULE_PARM_DESC(debug, "Enable verbose debug messages");
|
||||
|
||||
MODULE_DESCRIPTION("Samsung s5h1432 DVB-T Demodulator driver");
|
||||
MODULE_AUTHOR("Bill Liu");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
/*
|
||||
* Local variables:
|
||||
* c-basic-offset: 8
|
||||
*/
|
||||
96
drivers/media/dvb/frontends/s5h1432.h
Normal file
96
drivers/media/dvb/frontends/s5h1432.h
Normal file
|
|
@ -0,0 +1,96 @@
|
|||
/*
|
||||
Samsung s5h1432 VSB/QAM demodulator driver
|
||||
|
||||
Copyright (C) 2009 Bill Liu <Bill.Liu@Conexant.com>
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef __S5H1432_H__
|
||||
#define __S5H1432_H__
|
||||
|
||||
#include <linux/dvb/frontend.h>
|
||||
|
||||
#define S5H1432_I2C_TOP_ADDR (0x02 >> 1)
|
||||
|
||||
#define TAIWAN_HI_IF_FREQ_44_MHZ 44000000
|
||||
#define EUROPE_HI_IF_FREQ_36_MHZ 36000000
|
||||
#define IF_FREQ_6_MHZ 6000000
|
||||
#define IF_FREQ_3point3_MHZ 3300000
|
||||
#define IF_FREQ_3point5_MHZ 3500000
|
||||
#define IF_FREQ_4_MHZ 4000000
|
||||
|
||||
struct s5h1432_config {
|
||||
|
||||
/* serial/parallel output */
|
||||
#define S5H1432_PARALLEL_OUTPUT 0
|
||||
#define S5H1432_SERIAL_OUTPUT 1
|
||||
u8 output_mode;
|
||||
|
||||
/* GPIO Setting */
|
||||
#define S5H1432_GPIO_OFF 0
|
||||
#define S5H1432_GPIO_ON 1
|
||||
u8 gpio;
|
||||
|
||||
/* MPEG signal timing */
|
||||
#define S5H1432_MPEGTIMING_CONTINOUS_INVERTING_CLOCK 0
|
||||
#define S5H1432_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK 1
|
||||
#define S5H1432_MPEGTIMING_NONCONTINOUS_INVERTING_CLOCK 2
|
||||
#define S5H1432_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK 3
|
||||
u16 mpeg_timing;
|
||||
|
||||
/* IF Freq for QAM and VSB in KHz */
|
||||
#define S5H1432_IF_3250 3250
|
||||
#define S5H1432_IF_3500 3500
|
||||
#define S5H1432_IF_4000 4000
|
||||
#define S5H1432_IF_5380 5380
|
||||
#define S5H1432_IF_44000 44000
|
||||
#define S5H1432_VSB_IF_DEFAULT s5h1432_IF_44000
|
||||
#define S5H1432_QAM_IF_DEFAULT s5h1432_IF_44000
|
||||
u16 qam_if;
|
||||
u16 vsb_if;
|
||||
|
||||
/* Spectral Inversion */
|
||||
#define S5H1432_INVERSION_OFF 0
|
||||
#define S5H1432_INVERSION_ON 1
|
||||
u8 inversion;
|
||||
|
||||
/* Return lock status based on tuner lock, or demod lock */
|
||||
#define S5H1432_TUNERLOCKING 0
|
||||
#define S5H1432_DEMODLOCKING 1
|
||||
u8 status_mode;
|
||||
};
|
||||
|
||||
#if defined(CONFIG_DVB_S5H1432) || \
|
||||
(defined(CONFIG_DVB_S5H1432_MODULE) && defined(MODULE))
|
||||
extern struct dvb_frontend *s5h1432_attach(const struct s5h1432_config *config,
|
||||
struct i2c_adapter *i2c);
|
||||
#else
|
||||
static inline struct dvb_frontend *s5h1432_attach(
|
||||
const struct s5h1432_config *config,
|
||||
struct i2c_adapter *i2c)
|
||||
{
|
||||
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
|
||||
return NULL;
|
||||
}
|
||||
#endif /* CONFIG_DVB_s5h1432 */
|
||||
|
||||
#endif /* __s5h1432_H__ */
|
||||
|
||||
/*
|
||||
* Local variables:
|
||||
* c-basic-offset: 8
|
||||
*/
|
||||
Loading…
Reference in a new issue