Merge branch 'topic/stowe-cap-cleanup' into next
* topic/stowe-cap-cleanup: PCI: remove redundant capabilities checking in pci_{save, restore}_pcie_state PCI: add pci_pcie_cap2() check for PCIe feature capabilities >= v2 PCI: remove redundant checking in PCI Express capability routines PCI: make pci_ltr_supported() static
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47fcb6da65
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@ -253,6 +253,38 @@ int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
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return pos;
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}
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/**
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* pci_pcie_cap2 - query for devices' PCI_CAP_ID_EXP v2 capability structure
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* @dev: PCI device to check
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*
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* Like pci_pcie_cap() but also checks that the PCIe capability version is
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* >= 2. Note that v1 capability structures could be sparse in that not
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* all register fields were required. v2 requires the entire structure to
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* be present size wise, while still allowing for non-implemented registers
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* to exist but they must be hardwired to 0.
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*
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* Due to the differences in the versions of capability structures, one
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* must be careful not to try and access non-existant registers that may
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* exist in early versions - v1 - of Express devices.
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*
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* Returns the offset of the PCIe capability structure as long as the
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* capability version is >= 2; otherwise 0 is returned.
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*/
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static int pci_pcie_cap2(struct pci_dev *dev)
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{
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u16 flags;
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int pos;
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pos = pci_pcie_cap(dev);
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if (pos) {
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pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
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if ((flags & PCI_EXP_FLAGS_VERS) < 2)
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pos = 0;
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}
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return pos;
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}
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/**
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* pci_find_ext_capability - Find an extended capability
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* @dev: PCI device to query
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@ -755,12 +787,6 @@ EXPORT_SYMBOL(pci_choose_state);
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((flags & PCI_EXP_FLAGS_VERS) > 1 || \
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(type == PCI_EXP_TYPE_ROOT_PORT || \
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type == PCI_EXP_TYPE_RC_EC))
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#define pcie_cap_has_devctl2(type, flags) \
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((flags & PCI_EXP_FLAGS_VERS) > 1)
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#define pcie_cap_has_lnkctl2(type, flags) \
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((flags & PCI_EXP_FLAGS_VERS) > 1)
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#define pcie_cap_has_sltctl2(type, flags) \
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((flags & PCI_EXP_FLAGS_VERS) > 1)
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static struct pci_cap_saved_state *pci_find_saved_cap(
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struct pci_dev *pci_dev, char cap)
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@ -803,13 +829,14 @@ static int pci_save_pcie_state(struct pci_dev *dev)
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pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
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if (pcie_cap_has_rtctl(dev->pcie_type, flags))
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pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
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if (pcie_cap_has_devctl2(dev->pcie_type, flags))
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pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
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if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
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pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
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if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
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pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
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pos = pci_pcie_cap2(dev);
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if (!pos)
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return 0;
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pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
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pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
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pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
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return 0;
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}
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@ -836,12 +863,14 @@ static void pci_restore_pcie_state(struct pci_dev *dev)
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pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
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if (pcie_cap_has_rtctl(dev->pcie_type, flags))
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pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
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if (pcie_cap_has_devctl2(dev->pcie_type, flags))
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pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
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if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
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pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
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if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
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pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
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pos = pci_pcie_cap2(dev);
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if (!pos)
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return;
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pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
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pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
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pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
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}
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@ -1916,7 +1945,7 @@ void pci_enable_ari(struct pci_dev *dev)
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{
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int pos;
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u32 cap;
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u16 flags, ctrl;
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u16 ctrl;
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struct pci_dev *bridge;
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if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
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@ -1927,18 +1956,14 @@ void pci_enable_ari(struct pci_dev *dev)
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return;
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bridge = dev->bus->self;
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if (!bridge || !pci_is_pcie(bridge))
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if (!bridge)
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return;
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pos = pci_pcie_cap(bridge);
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/* ARI is a PCIe cap v2 feature */
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pos = pci_pcie_cap2(bridge);
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if (!pos)
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return;
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/* ARI is a PCIe v2 feature */
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pci_read_config_word(bridge, pos + PCI_EXP_FLAGS, &flags);
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if ((flags & PCI_EXP_FLAGS_VERS) < 2)
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return;
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pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
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if (!(cap & PCI_EXP_DEVCAP2_ARI))
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return;
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@ -1951,7 +1976,7 @@ void pci_enable_ari(struct pci_dev *dev)
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}
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/**
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* pci_enable_ido - enable ID-based ordering on a device
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* pci_enable_ido - enable ID-based Ordering on a device
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* @dev: the PCI device
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* @type: which types of IDO to enable
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*
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@ -1964,7 +1989,8 @@ void pci_enable_ido(struct pci_dev *dev, unsigned long type)
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int pos;
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u16 ctrl;
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pos = pci_pcie_cap(dev);
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/* ID-based Ordering is a PCIe cap v2 feature */
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pos = pci_pcie_cap2(dev);
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if (!pos)
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return;
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@ -1987,10 +2013,8 @@ void pci_disable_ido(struct pci_dev *dev, unsigned long type)
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int pos;
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u16 ctrl;
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if (!pci_is_pcie(dev))
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return;
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pos = pci_pcie_cap(dev);
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/* ID-based Ordering is a PCIe cap v2 feature */
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pos = pci_pcie_cap2(dev);
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if (!pos)
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return;
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@ -2029,10 +2053,8 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
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u16 ctrl;
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int ret;
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if (!pci_is_pcie(dev))
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return -ENOTSUPP;
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pos = pci_pcie_cap(dev);
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/* OBFF is a PCIe cap v2 feature */
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pos = pci_pcie_cap2(dev);
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if (!pos)
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return -ENOTSUPP;
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@ -2082,10 +2104,8 @@ void pci_disable_obff(struct pci_dev *dev)
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int pos;
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u16 ctrl;
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if (!pci_is_pcie(dev))
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return;
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pos = pci_pcie_cap(dev);
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/* OBFF is a PCIe cap v2 feature */
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pos = pci_pcie_cap2(dev);
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if (!pos)
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return;
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@ -2102,15 +2122,13 @@ EXPORT_SYMBOL(pci_disable_obff);
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* RETURNS:
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* True if @dev supports latency tolerance reporting, false otherwise.
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*/
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bool pci_ltr_supported(struct pci_dev *dev)
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static bool pci_ltr_supported(struct pci_dev *dev)
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{
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int pos;
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u32 cap;
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if (!pci_is_pcie(dev))
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return false;
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pos = pci_pcie_cap(dev);
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/* LTR is a PCIe cap v2 feature */
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pos = pci_pcie_cap2(dev);
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if (!pos)
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return false;
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@ -2118,7 +2136,6 @@ bool pci_ltr_supported(struct pci_dev *dev)
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return cap & PCI_EXP_DEVCAP2_LTR;
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}
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EXPORT_SYMBOL(pci_ltr_supported);
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/**
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* pci_enable_ltr - enable latency tolerance reporting
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@ -2139,7 +2156,8 @@ int pci_enable_ltr(struct pci_dev *dev)
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if (!pci_ltr_supported(dev))
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return -ENOTSUPP;
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pos = pci_pcie_cap(dev);
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/* LTR is a PCIe cap v2 feature */
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pos = pci_pcie_cap2(dev);
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if (!pos)
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return -ENOTSUPP;
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@ -2174,7 +2192,8 @@ void pci_disable_ltr(struct pci_dev *dev)
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if (!pci_ltr_supported(dev))
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return;
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pos = pci_pcie_cap(dev);
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/* LTR is a PCIe cap v2 feature */
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pos = pci_pcie_cap2(dev);
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if (!pos)
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return;
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@ -911,7 +911,6 @@ enum pci_obff_signal_type {
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int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
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void pci_disable_obff(struct pci_dev *dev);
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bool pci_ltr_supported(struct pci_dev *dev);
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int pci_enable_ltr(struct pci_dev *dev);
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void pci_disable_ltr(struct pci_dev *dev);
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int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
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@ -521,6 +521,12 @@
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#define PCI_EXP_RTSTA 32 /* Root Status */
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#define PCI_EXP_RTSTA_PME 0x10000 /* PME status */
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#define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */
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/*
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* Note that the following PCI Express 'Capability Structure' registers
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* were introduced with 'Capability Version' 0x2 (v2). These registers
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* do not exist on devices with Capability Version 1. Use pci_pcie_cap2()
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* to use these fields safely.
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*/
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#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
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#define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */
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#define PCI_EXP_DEVCAP2_LTR 0x800 /* Latency tolerance reporting */
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