iwlwifi: move iwl_txq and substructures to a common trans header
The txq code is not directly related to the PCIe transport, so move the structures it uses to the common iwl-trans.h header. Signed-off-by: Mordechay Goodstein <mordechay.goodstein@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com> Link: https://lore.kernel.org/r/iwlwifi.20200529092401.d9d0082b8369.I8298f6e83804c1ea99217a79d95d23ef68b184d4@changeidalistair/sunxi64-5.8
Mordechay Goodstein
Luca Coelho
parent
6157624055
commit
4807e73685
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@ -795,6 +795,113 @@ struct iwl_trans_debug {
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u32 domains_bitmap;
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};
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struct iwl_dma_ptr {
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dma_addr_t dma;
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void *addr;
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size_t size;
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};
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struct iwl_cmd_meta {
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/* only for SYNC commands, iff the reply skb is wanted */
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struct iwl_host_cmd *source;
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u32 flags;
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u32 tbs;
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};
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/*
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* The FH will write back to the first TB only, so we need to copy some data
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* into the buffer regardless of whether it should be mapped or not.
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* This indicates how big the first TB must be to include the scratch buffer
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* and the assigned PN.
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* Since PN location is 8 bytes at offset 12, it's 20 now.
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* If we make it bigger then allocations will be bigger and copy slower, so
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* that's probably not useful.
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*/
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#define IWL_FIRST_TB_SIZE 20
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#define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64)
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struct iwl_pcie_txq_entry {
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void *cmd;
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struct sk_buff *skb;
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/* buffer to free after command completes */
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const void *free_buf;
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struct iwl_cmd_meta meta;
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};
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struct iwl_pcie_first_tb_buf {
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u8 buf[IWL_FIRST_TB_SIZE_ALIGN];
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};
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/**
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* struct iwl_txq - Tx Queue for DMA
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* @q: generic Rx/Tx queue descriptor
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* @tfds: transmit frame descriptors (DMA memory)
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* @first_tb_bufs: start of command headers, including scratch buffers, for
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* the writeback -- this is DMA memory and an array holding one buffer
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* for each command on the queue
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* @first_tb_dma: DMA address for the first_tb_bufs start
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* @entries: transmit entries (driver state)
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* @lock: queue lock
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* @stuck_timer: timer that fires if queue gets stuck
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* @trans: pointer back to transport (for timer)
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* @need_update: indicates need to update read/write index
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* @ampdu: true if this queue is an ampdu queue for an specific RA/TID
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* @wd_timeout: queue watchdog timeout (jiffies) - per queue
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* @frozen: tx stuck queue timer is frozen
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* @frozen_expiry_remainder: remember how long until the timer fires
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* @bc_tbl: byte count table of the queue (relevant only for gen2 transport)
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* @write_ptr: 1-st empty entry (index) host_w
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* @read_ptr: last used entry (index) host_r
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* @dma_addr: physical addr for BD's
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* @n_window: safe queue window
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* @id: queue id
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* @low_mark: low watermark, resume queue if free space more than this
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* @high_mark: high watermark, stop queue if free space less than this
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*
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* A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
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* descriptors) and required locking structures.
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*
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* Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware
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* always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless
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* there might be HW changes in the future). For the normal TX
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* queues, n_window, which is the size of the software queue data
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* is also 256; however, for the command queue, n_window is only
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* 32 since we don't need so many commands pending. Since the HW
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* still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256.
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* This means that we end up with the following:
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* HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
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* SW entries: | 0 | ... | 31 |
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* where N is a number between 0 and 7. This means that the SW
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* data is a window overlayed over the HW queue.
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*/
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struct iwl_txq {
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void *tfds;
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struct iwl_pcie_first_tb_buf *first_tb_bufs;
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dma_addr_t first_tb_dma;
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struct iwl_pcie_txq_entry *entries;
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/* lock for syncing changes on the queue */
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spinlock_t lock;
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unsigned long frozen_expiry_remainder;
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struct timer_list stuck_timer;
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struct iwl_trans *trans;
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bool need_update;
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bool frozen;
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bool ampdu;
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int block;
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unsigned long wd_timeout;
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struct sk_buff_head overflow_q;
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struct iwl_dma_ptr bc_tbl;
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int write_ptr;
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int read_ptr;
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dma_addr_t dma_addr;
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int n_window;
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u32 id;
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int low_mark;
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int high_mark;
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bool overflow_tx;
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};
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/**
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* struct iwl_trans - transport common data
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*
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@ -246,12 +246,6 @@ struct iwl_rb_allocator {
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struct work_struct rx_alloc;
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};
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struct iwl_dma_ptr {
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dma_addr_t dma;
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void *addr;
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size_t size;
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};
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/**
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* iwl_queue_inc_wrap - increment queue index, wrap back to beginning
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* @index -- current index
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@ -290,107 +284,6 @@ static inline int iwl_queue_dec_wrap(struct iwl_trans *trans, int index)
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(trans->trans_cfg->base_params->max_tfd_queue_size - 1);
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}
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struct iwl_cmd_meta {
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/* only for SYNC commands, iff the reply skb is wanted */
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struct iwl_host_cmd *source;
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u32 flags;
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u32 tbs;
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};
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/*
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* The FH will write back to the first TB only, so we need to copy some data
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* into the buffer regardless of whether it should be mapped or not.
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* This indicates how big the first TB must be to include the scratch buffer
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* and the assigned PN.
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* Since PN location is 8 bytes at offset 12, it's 20 now.
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* If we make it bigger then allocations will be bigger and copy slower, so
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* that's probably not useful.
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*/
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#define IWL_FIRST_TB_SIZE 20
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#define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64)
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struct iwl_pcie_txq_entry {
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void *cmd;
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struct sk_buff *skb;
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/* buffer to free after command completes */
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const void *free_buf;
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struct iwl_cmd_meta meta;
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};
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struct iwl_pcie_first_tb_buf {
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u8 buf[IWL_FIRST_TB_SIZE_ALIGN];
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};
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/**
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* struct iwl_txq - Tx Queue for DMA
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* @q: generic Rx/Tx queue descriptor
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* @tfds: transmit frame descriptors (DMA memory)
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* @first_tb_bufs: start of command headers, including scratch buffers, for
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* the writeback -- this is DMA memory and an array holding one buffer
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* for each command on the queue
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* @first_tb_dma: DMA address for the first_tb_bufs start
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* @entries: transmit entries (driver state)
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* @lock: queue lock
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* @stuck_timer: timer that fires if queue gets stuck
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* @trans: pointer back to transport (for timer)
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* @need_update: indicates need to update read/write index
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* @ampdu: true if this queue is an ampdu queue for an specific RA/TID
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* @wd_timeout: queue watchdog timeout (jiffies) - per queue
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* @frozen: tx stuck queue timer is frozen
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* @frozen_expiry_remainder: remember how long until the timer fires
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* @bc_tbl: byte count table of the queue (relevant only for gen2 transport)
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* @write_ptr: 1-st empty entry (index) host_w
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* @read_ptr: last used entry (index) host_r
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* @dma_addr: physical addr for BD's
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* @n_window: safe queue window
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* @id: queue id
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* @low_mark: low watermark, resume queue if free space more than this
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* @high_mark: high watermark, stop queue if free space less than this
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*
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* A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
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* descriptors) and required locking structures.
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*
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* Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware
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* always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless
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* there might be HW changes in the future). For the normal TX
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* queues, n_window, which is the size of the software queue data
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* is also 256; however, for the command queue, n_window is only
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* 32 since we don't need so many commands pending. Since the HW
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* still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256.
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* This means that we end up with the following:
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* HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
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* SW entries: | 0 | ... | 31 |
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* where N is a number between 0 and 7. This means that the SW
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* data is a window overlayed over the HW queue.
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*/
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struct iwl_txq {
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void *tfds;
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struct iwl_pcie_first_tb_buf *first_tb_bufs;
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dma_addr_t first_tb_dma;
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struct iwl_pcie_txq_entry *entries;
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spinlock_t lock;
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unsigned long frozen_expiry_remainder;
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struct timer_list stuck_timer;
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struct iwl_trans *trans;
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bool need_update;
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bool frozen;
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bool ampdu;
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int block;
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unsigned long wd_timeout;
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struct sk_buff_head overflow_q;
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struct iwl_dma_ptr bc_tbl;
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int write_ptr;
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int read_ptr;
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dma_addr_t dma_addr;
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int n_window;
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u32 id;
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int low_mark;
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int high_mark;
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bool overflow_tx;
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};
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static inline dma_addr_t
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iwl_pcie_get_first_tb_dma(struct iwl_txq *txq, int idx)
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{
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