ALSA: x86: Remove v1 ops and structs
The v1 code refers to Medfield/Clovertrail. It's not used at all in the current driver, and probably won't be ever. Let's clean this up, then we can go to the next stage of cleanup tasks. Signed-off-by: Takashi Iwai <tiwai@suse.de>hifive-unleashed-5.1
Takashi Iwai
parent
716733032a
commit
4812dcc437
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@ -280,23 +280,12 @@ static int had_read_modify_aud_config_v2(struct snd_pcm_substream *substream,
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return had_read_modify(AUD_CONFIG, data, mask);
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}
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static void snd_intelhad_enable_audio_v1(struct snd_pcm_substream *substream,
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u8 enable)
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{
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had_read_modify(AUD_CONFIG, enable, BIT(0));
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}
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static void snd_intelhad_enable_audio_v2(struct snd_pcm_substream *substream,
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u8 enable)
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{
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had_read_modify_aud_config_v2(substream, enable, BIT(0));
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}
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static void snd_intelhad_reset_audio_v1(u8 reset)
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{
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had_write_register(AUD_HDMI_STATUS, reset);
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}
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static void snd_intelhad_reset_audio_v2(u8 reset)
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{
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had_write_register(AUD_HDMI_STATUS_v2, reset);
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@ -320,7 +309,7 @@ static int had_prog_status_reg(struct snd_pcm_substream *substream,
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IEC958_AES0_NONAUDIO)>>1;
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ch_stat0.status_0_regx.clk_acc = (intelhaddata->aes_bits &
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IEC958_AES3_CON_CLOCK)>>4;
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cfg_val.cfg_regx.val_bit = ch_stat0.status_0_regx.lpcm_id;
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cfg_val.cfg_regx_v2.val_bit = ch_stat0.status_0_regx.lpcm_id;
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switch (substream->runtime->rate) {
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case AUD_SAMPLE_RATE_32:
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@ -401,58 +390,6 @@ static int snd_intelhad_prog_audio_ctrl_v2(struct snd_pcm_substream *substream,
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return 0;
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}
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/**
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* function to initialize audio
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* registers and buffer confgiuration registers
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* This function is called in the prepare callback
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*/
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static int snd_intelhad_prog_audio_ctrl_v1(struct snd_pcm_substream *substream,
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struct snd_intelhad *intelhaddata)
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{
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union aud_cfg cfg_val = {.cfg_regval = 0};
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union aud_buf_config buf_cfg = {.buf_cfgval = 0};
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u8 channels;
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had_prog_status_reg(substream, intelhaddata);
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buf_cfg.buf_cfg_regx.fifo_width = FIFO_THRESHOLD;
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buf_cfg.buf_cfg_regx.aud_delay = 0;
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had_write_register(AUD_BUF_CONFIG, buf_cfg.buf_cfgval);
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channels = substream->runtime->channels;
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switch (channels) {
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case 1:
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case 2:
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cfg_val.cfg_regx.num_ch = CH_STEREO;
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cfg_val.cfg_regx.layout = LAYOUT0;
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break;
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case 3:
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case 4:
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cfg_val.cfg_regx.num_ch = CH_THREE_FOUR;
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cfg_val.cfg_regx.layout = LAYOUT1;
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break;
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case 5:
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case 6:
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cfg_val.cfg_regx.num_ch = CH_FIVE_SIX;
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cfg_val.cfg_regx.layout = LAYOUT1;
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break;
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case 7:
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case 8:
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cfg_val.cfg_regx.num_ch = CH_SEVEN_EIGHT;
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cfg_val.cfg_regx.layout = LAYOUT1;
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break;
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}
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cfg_val.cfg_regx.val_bit = 1;
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had_write_register(AUD_CONFIG, cfg_val.cfg_regval);
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return 0;
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}
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/*
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* Compute derived values in channel_allocations[].
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*/
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@ -659,56 +596,6 @@ static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata,
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return 0;
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}
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/**
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* snd_intelhad_prog_dip_v1 - to initialize Data Island Packets registers
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*
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* @substream:substream for which the prepare function is called
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* @intelhaddata:substream private data
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*
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* This function is called in the prepare callback
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*/
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static void snd_intelhad_prog_dip_v1(struct snd_pcm_substream *substream,
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struct snd_intelhad *intelhaddata)
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{
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int i;
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union aud_ctrl_st ctrl_state = {.ctrl_val = 0};
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union aud_info_frame2 frame2 = {.fr2_val = 0};
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union aud_info_frame3 frame3 = {.fr3_val = 0};
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u8 checksum = 0;
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int channels;
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channels = substream->runtime->channels;
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had_write_register(AUD_CNTL_ST, ctrl_state.ctrl_val);
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frame2.fr2_regx.chnl_cnt = substream->runtime->channels - 1;
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frame3.fr3_regx.chnl_alloc = snd_intelhad_channel_allocation(
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intelhaddata, channels);
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/*Calculte the byte wide checksum for all valid DIP words*/
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for (i = 0; i < BYTES_PER_WORD; i++)
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checksum += (HDMI_INFO_FRAME_WORD1 >> i*BITS_PER_BYTE) & MASK_BYTE0;
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for (i = 0; i < BYTES_PER_WORD; i++)
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checksum += (frame2.fr2_val >> i*BITS_PER_BYTE) & MASK_BYTE0;
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for (i = 0; i < BYTES_PER_WORD; i++)
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checksum += (frame3.fr3_val >> i*BITS_PER_BYTE) & MASK_BYTE0;
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frame2.fr2_regx.chksum = -(checksum);
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had_write_register(AUD_HDMIW_INFOFR, HDMI_INFO_FRAME_WORD1);
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had_write_register(AUD_HDMIW_INFOFR, frame2.fr2_val);
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had_write_register(AUD_HDMIW_INFOFR, frame3.fr3_val);
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/* program remaining DIP words with zero */
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for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++)
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had_write_register(AUD_HDMIW_INFOFR, 0x0);
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ctrl_state.ctrl_regx.dip_freq = 1;
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ctrl_state.ctrl_regx.dip_en_sta = 1;
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had_write_register(AUD_CNTL_ST, ctrl_state.ctrl_val);
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}
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/**
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* snd_intelhad_prog_dip_v2 - to initialize Data Island Packets registers
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*
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@ -928,32 +815,6 @@ static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate)
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return maud_val;
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}
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/**
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* snd_intelhad_prog_cts_v1 - Program HDMI audio CTS value
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*
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* @aud_samp_freq: sampling frequency of audio data
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* @tmds: sampling frequency of the display data
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* @n_param: N value, depends on aud_samp_freq
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* @intelhaddata:substream private data
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*
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* Program CTS register based on the audio and display sampling frequency
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*/
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static void snd_intelhad_prog_cts_v1(u32 aud_samp_freq, u32 tmds,
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u32 link_rate, u32 n_param,
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struct snd_intelhad *intelhaddata)
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{
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u32 cts_val;
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u64 dividend, divisor;
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/* Calculate CTS according to HDMI 1.3a spec*/
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dividend = (u64)tmds * n_param*1000;
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divisor = 128 * aud_samp_freq;
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cts_val = div64_u64(dividend, divisor);
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pr_debug("TMDS value=%d, N value=%d, CTS Value=%d\n",
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tmds, n_param, cts_val);
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had_write_register(AUD_HDMI_CTS, (BIT(20) | cts_val));
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}
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/**
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* snd_intelhad_prog_cts_v2 - Program HDMI audio CTS value
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*
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@ -1026,31 +887,6 @@ static int had_calculate_n_value(u32 aud_samp_freq)
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return n_val;
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}
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/**
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* snd_intelhad_prog_n_v1 - Program HDMI audio N value
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*
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* @aud_samp_freq: sampling frequency of audio data
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* @n_param: N value, depends on aud_samp_freq
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* @intelhaddata:substream private data
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*
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* This function is called in the prepare callback.
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* It programs based on the audio and display sampling frequency
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*/
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static int snd_intelhad_prog_n_v1(u32 aud_samp_freq, u32 *n_param,
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struct snd_intelhad *intelhaddata)
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{
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s32 n_val;
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n_val = had_calculate_n_value(aud_samp_freq);
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if (n_val < 0)
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return n_val;
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had_write_register(AUD_N_ENABLE, (BIT(20) | n_val));
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*n_param = n_val;
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return 0;
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}
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/**
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* snd_intelhad_prog_n_v2 - Program HDMI audio N value
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*
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@ -1087,35 +923,6 @@ static int snd_intelhad_prog_n_v2(u32 aud_samp_freq, u32 *n_param,
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return 0;
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}
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static void had_clear_underrun_intr_v1(struct snd_intelhad *intelhaddata)
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{
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u32 hdmi_status, i = 0;
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/* Handle Underrun interrupt within Audio Unit */
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had_write_register(AUD_CONFIG, 0);
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/* Reset buffer pointers */
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had_write_register(AUD_HDMI_STATUS, 1);
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had_write_register(AUD_HDMI_STATUS, 0);
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/**
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* The interrupt status 'sticky' bits might not be cleared by
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* setting '1' to that bit once...
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*/
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do { /* clear bit30, 31 AUD_HDMI_STATUS */
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had_read_register(AUD_HDMI_STATUS, &hdmi_status);
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pr_debug("HDMI status =0x%x\n", hdmi_status);
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if (hdmi_status & AUD_CONFIG_MASK_UNDERRUN) {
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i++;
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hdmi_status &= (AUD_CONFIG_MASK_SRDBG |
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AUD_CONFIG_MASK_FUNCRST);
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hdmi_status |= ~AUD_CONFIG_MASK_UNDERRUN;
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had_write_register(AUD_HDMI_STATUS, hdmi_status);
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} else
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break;
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} while (i < MAX_CNT);
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if (i >= MAX_CNT)
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pr_err("Unable to clear UNDERRUN bits\n");
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}
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static void had_clear_underrun_intr_v2(struct snd_intelhad *intelhaddata)
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{
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u32 hdmi_status, i = 0;
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@ -1775,16 +1582,6 @@ static struct snd_intel_had_interface had_interface = {
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.resume = hdmi_audio_resume,
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};
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static struct had_ops had_ops_v1 = {
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.enable_audio = snd_intelhad_enable_audio_v1,
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.reset_audio = snd_intelhad_reset_audio_v1,
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.prog_n = snd_intelhad_prog_n_v1,
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.prog_cts = snd_intelhad_prog_cts_v1,
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.audio_ctrl = snd_intelhad_prog_audio_ctrl_v1,
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.prog_dip = snd_intelhad_prog_dip_v1,
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.handle_underrun = had_clear_underrun_intr_v1,
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};
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static struct had_ops had_ops_v2 = {
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.enable_audio = snd_intelhad_enable_audio_v2,
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.reset_audio = snd_intelhad_reset_audio_v2,
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@ -1934,7 +1731,6 @@ int hdmi_audio_probe(void *deviceptr)
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}
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intelhaddata->hw_silence = 1;
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had_ops_v1 = had_ops_v1; /* unused */
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intelhaddata->ops = &had_ops_v2;
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return retval;
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@ -358,19 +358,6 @@ struct channel_map_table {
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*
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*/
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union aud_cfg {
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struct {
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u32 aud_en:1;
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u32 layout:1;
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u32 fmt:2;
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u32 num_ch:2;
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u32 rsvd0:1;
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u32 set:1;
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u32 flat:1;
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u32 val_bit:1;
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u32 user_bit:1;
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u32 underrun:1;
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u32 rsvd1:20;
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} cfg_regx;
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struct {
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u32 aud_en:1;
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u32 layout:1;
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@ -438,11 +425,6 @@ union aud_ch_status_1 {
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*
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*/
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union aud_hdmi_cts {
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struct {
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u32 cts_val:20;
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u32 en_cts_prog:1;
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u32 rsvd:11;
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} cts_regx;
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struct {
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u32 cts_val:24;
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u32 en_cts_prog:1;
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@ -459,11 +441,6 @@ union aud_hdmi_cts {
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*
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*/
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union aud_hdmi_n_enable {
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struct {
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u32 n_val:20;
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u32 en_n_prog:1;
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u32 rsvd:11;
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} n_regx;
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struct {
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u32 n_val:24;
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u32 en_n_prog:1;
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@ -480,12 +457,6 @@ union aud_hdmi_n_enable {
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*
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*/
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union aud_buf_config {
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struct {
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u32 fifo_width:8;
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u32 rsvd0:8;
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u32 aud_delay:8;
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u32 rsvd1:8;
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} buf_cfg_regx;
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struct {
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u32 audio_fifo_watermark:8;
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u32 dma_fifo_watermark:3;
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