Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel
Just a few small things: - 2x workaround bits from Chris to fix up the new scanline waits enabled in 3.8 on snb. People who've been struck by this on dual-screen also need to upgrade the ddx. - Dump the kernel version into i915_error_state, we've had a few mixups there recently. - Disable gfx DMAR on gen4 devices, acked by David Woodhouse. * 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel: drm/i915: dump UTS_RELEASE into the error_state iommu/intel: disable DMAR for g4x integrated gfx drm/i915: GFX_MODE Flush TLB Invalidate Mode must be '1' for scanline waits drm/i915: Disable AsyncFlip performance optimisations
This commit is contained in:
commit
483674325f
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@ -30,6 +30,7 @@
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#include <linux/debugfs.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <generated/utsrelease.h>
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#include <drm/drmP.h>
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#include "intel_drv.h"
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#include "intel_ringbuffer.h"
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@ -690,6 +691,7 @@ static int i915_error_state(struct seq_file *m, void *unused)
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seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
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error->time.tv_usec);
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seq_printf(m, "Kernel: " UTS_RELEASE);
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seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
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seq_printf(m, "EIR: 0x%08x\n", error->eir);
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seq_printf(m, "IER: 0x%08x\n", error->ier);
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@ -533,6 +533,7 @@
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#define MI_MODE 0x0209c
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# define VS_TIMER_DISPATCH (1 << 6)
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# define MI_FLUSH_ENABLE (1 << 12)
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# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
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#define GEN6_GT_MODE 0x20d0
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#define GEN6_GT_MODE_HI (1 << 9)
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@ -505,13 +505,25 @@ static int init_render_ring(struct intel_ring_buffer *ring)
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struct drm_i915_private *dev_priv = dev->dev_private;
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int ret = init_ring_common(ring);
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if (INTEL_INFO(dev)->gen > 3) {
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if (INTEL_INFO(dev)->gen > 3)
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I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
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if (IS_GEN7(dev))
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I915_WRITE(GFX_MODE_GEN7,
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_MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
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_MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
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}
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/* We need to disable the AsyncFlip performance optimisations in order
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* to use MI_WAIT_FOR_EVENT within the CS. It should already be
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* programmed to '1' on all products.
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*/
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if (INTEL_INFO(dev)->gen >= 6)
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I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
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/* Required for the hardware to program scanline values for waiting */
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if (INTEL_INFO(dev)->gen == 6)
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I915_WRITE(GFX_MODE,
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_MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
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if (IS_GEN7(dev))
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I915_WRITE(GFX_MODE_GEN7,
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_MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
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_MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
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if (INTEL_INFO(dev)->gen >= 5) {
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ret = init_pipe_control(ring);
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@ -4234,6 +4234,21 @@ static struct iommu_ops intel_iommu_ops = {
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.pgsize_bitmap = INTEL_IOMMU_PGSIZES,
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};
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static void quirk_iommu_g4x_gfx(struct pci_dev *dev)
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{
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/* G4x/GM45 integrated gfx dmar support is totally busted. */
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printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
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dmar_map_gfx = 0;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx);
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static void quirk_iommu_rwbf(struct pci_dev *dev)
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{
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/*
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@ -4242,12 +4257,6 @@ static void quirk_iommu_rwbf(struct pci_dev *dev)
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*/
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printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
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rwbf_quirk = 1;
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/* https://bugzilla.redhat.com/show_bug.cgi?id=538163 */
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if (dev->revision == 0x07) {
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printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
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dmar_map_gfx = 0;
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
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