redonkable
/
alistair23-linux
1
0
Fork 0
Code Releases Activity

MLK-22936 clk: imx: Only save DC SS clock using non-cached clock rate 

Display sub-system has special clock settings in SCFW, the
bypassed clock is used instead of PLL in Linux kernel clock
tree, so when saving clock rate, need to save non-cached clock
rate for Display sub-system's bypass clocks, and other clocks
still use the cached clock rate which is with runtime PM ON.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Tested-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Anson Huang 2019-11-08 16:29:28 +08:00 committed by Dong Aisheng
parent bae5f64837
commit 4872753779
1 changed files with 8 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/clk/imx/clk-scu.c
View File

@ -549,7 +549,14 @@ int __maybe_unused imx_clk_scu_suspend(struct device *dev)
(rsrc_id == IMX_SC_R_A72))
return 0;
clk->rate = clk_hw_get_rate(&clk->hw);
/* DC SS needs to handle bypass clock using non-cached clock rate */
if (clk->rsrc_id == IMX_SC_R_DC_0_VIDEO0 ||
clk->rsrc_id == IMX_SC_R_DC_0_VIDEO1 ||
clk->rsrc_id == IMX_SC_R_DC_1_VIDEO0 ||
clk->rsrc_id == IMX_SC_R_DC_1_VIDEO1)
clk->rate = clk_scu_recalc_rate(&clk->hw, 0);
else
clk->rate = clk_hw_get_rate(&clk->hw);
clk->is_enabled = clk_hw_is_enabled(&clk->hw);
if (clk->rate)