MTD:
* sm_ftl: Fix NULL pointer warning. Raw NAND: * Cadence: fix compile testing. * STM32: Avoid locking. Onenand: * Fix several sparse/build warnings. SPI-NOR: * Add a flag to fix interaction with Micron parts. -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEE9HuaYnbmDhq/XIDIJWrqGEe9VoQFAl4YipIACgkQJWrqGEe9 VoTr/Af9GDYEaD5ZnYeOwTSs43Cd62K7wzPar9tE20xu5VVmPXmyIgSmxyoPXpjh O89xxahrG4sD0vokSWstjgZVTzBEu2DHkeOsjD6j7buXlv5LN8o4dAqw7k6+Hle5 T5qHZogcO2HK+4OijIP6xJ6hQMGz4YxZvhw34zEqdPYivxTK8X3EDEuQDns9bMUr nPOjCYhOoR//iIRUA+l78VEnA2unnGGhaQhBxGm43xwqYLrOMsmz859pjbt1DGob B3w2MlJ33ADBhA3/7PswAb8Otz6yPT8eq/8a8Pl+t9SZIwgZGBnjv/kzkBaZQ0r7 UCe2aVD97l5OkIBoIfPA+thbavrHwQ== =TapA -----END PGP SIGNATURE----- Merge tag 'mtd/fixes-for-5.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD fixes from Miquel Raynal: "MTD: - sm_ftl: Fix NULL pointer warning. Raw NAND: - Cadence: fix compile testing. - STM32: Avoid locking. Onenand: - Fix several sparse/build warnings. SPI-NOR: - Add a flag to fix interaction with Micron parts" * tag 'mtd/fixes-for-5.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: mtd: spi-nor: Fix the writing of the Status Register on micron flashes mtd: sm_ftl: fix NULL pointer warning mtd: onenand: omap2: Pass correct flags for prep_dma_memcpy mtd: onenand: samsung: Fix iomem access with regular memcpy mtd: onenand: omap2: Fix errors in style mtd: cadence: Fix cast to pointer from integer of different size warning mtd: rawnand: stm32_fmc2: avoid to lock the CPU bus
This commit is contained in:
commit
4936ce17bf
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@ -148,13 +148,13 @@ static int omap2_onenand_wait(struct mtd_info *mtd, int state)
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unsigned long timeout;
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unsigned long timeout;
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u32 syscfg;
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u32 syscfg;
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if (state == FL_RESETING || state == FL_PREPARING_ERASE ||
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if (state == FL_RESETTING || state == FL_PREPARING_ERASE ||
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state == FL_VERIFYING_ERASE) {
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state == FL_VERIFYING_ERASE) {
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int i = 21;
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int i = 21;
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unsigned int intr_flags = ONENAND_INT_MASTER;
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unsigned int intr_flags = ONENAND_INT_MASTER;
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switch (state) {
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switch (state) {
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case FL_RESETING:
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case FL_RESETTING:
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intr_flags |= ONENAND_INT_RESET;
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intr_flags |= ONENAND_INT_RESET;
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break;
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break;
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case FL_PREPARING_ERASE:
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case FL_PREPARING_ERASE:
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@ -328,7 +328,8 @@ static inline int omap2_onenand_dma_transfer(struct omap2_onenand *c,
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struct dma_async_tx_descriptor *tx;
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struct dma_async_tx_descriptor *tx;
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dma_cookie_t cookie;
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dma_cookie_t cookie;
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tx = dmaengine_prep_dma_memcpy(c->dma_chan, dst, src, count, 0);
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tx = dmaengine_prep_dma_memcpy(c->dma_chan, dst, src, count,
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DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
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if (!tx) {
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if (!tx) {
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dev_err(&c->pdev->dev, "Failed to prepare DMA memcpy\n");
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dev_err(&c->pdev->dev, "Failed to prepare DMA memcpy\n");
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return -EIO;
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return -EIO;
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@ -375,7 +376,7 @@ static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
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* context fallback to PIO mode.
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* context fallback to PIO mode.
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*/
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*/
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if (!virt_addr_valid(buf) || bram_offset & 3 || (size_t)buf & 3 ||
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if (!virt_addr_valid(buf) || bram_offset & 3 || (size_t)buf & 3 ||
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count < 384 || in_interrupt() || oops_in_progress )
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count < 384 || in_interrupt() || oops_in_progress)
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goto out_copy;
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goto out_copy;
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xtra = count & 3;
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xtra = count & 3;
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@ -422,7 +423,7 @@ static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
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* context fallback to PIO mode.
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* context fallback to PIO mode.
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*/
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*/
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if (!virt_addr_valid(buf) || bram_offset & 3 || (size_t)buf & 3 ||
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if (!virt_addr_valid(buf) || bram_offset & 3 || (size_t)buf & 3 ||
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count < 384 || in_interrupt() || oops_in_progress )
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count < 384 || in_interrupt() || oops_in_progress)
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goto out_copy;
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goto out_copy;
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dma_src = dma_map_single(dev, buf, count, DMA_TO_DEVICE);
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dma_src = dma_map_single(dev, buf, count, DMA_TO_DEVICE);
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@ -528,7 +529,8 @@ static int omap2_onenand_probe(struct platform_device *pdev)
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c->gpmc_cs, c->phys_base, c->onenand.base,
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c->gpmc_cs, c->phys_base, c->onenand.base,
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c->dma_chan ? "DMA" : "PIO");
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c->dma_chan ? "DMA" : "PIO");
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if ((r = onenand_scan(&c->mtd, 1)) < 0)
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r = onenand_scan(&c->mtd, 1);
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if (r < 0)
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goto err_release_dma;
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goto err_release_dma;
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freq = omap2_onenand_get_freq(c->onenand.version_id);
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freq = omap2_onenand_get_freq(c->onenand.version_id);
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@ -2853,7 +2853,7 @@ static int onenand_otp_write_oob_nolock(struct mtd_info *mtd, loff_t to,
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/* Exit OTP access mode */
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/* Exit OTP access mode */
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this->command(mtd, ONENAND_CMD_RESET, 0, 0);
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this->command(mtd, ONENAND_CMD_RESET, 0, 0);
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this->wait(mtd, FL_RESETING);
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this->wait(mtd, FL_RESETTING);
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status = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
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status = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
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status &= 0x60;
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status &= 0x60;
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@ -2924,7 +2924,7 @@ static int do_otp_read(struct mtd_info *mtd, loff_t from, size_t len,
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/* Exit OTP access mode */
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/* Exit OTP access mode */
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this->command(mtd, ONENAND_CMD_RESET, 0, 0);
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this->command(mtd, ONENAND_CMD_RESET, 0, 0);
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this->wait(mtd, FL_RESETING);
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this->wait(mtd, FL_RESETTING);
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return ret;
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return ret;
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}
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}
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@ -2968,7 +2968,7 @@ static int do_otp_write(struct mtd_info *mtd, loff_t to, size_t len,
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/* Exit OTP access mode */
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/* Exit OTP access mode */
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this->command(mtd, ONENAND_CMD_RESET, 0, 0);
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this->command(mtd, ONENAND_CMD_RESET, 0, 0);
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this->wait(mtd, FL_RESETING);
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this->wait(mtd, FL_RESETTING);
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return ret;
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return ret;
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}
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}
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@ -3008,7 +3008,7 @@ static int do_otp_lock(struct mtd_info *mtd, loff_t from, size_t len,
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/* Exit OTP access mode */
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/* Exit OTP access mode */
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this->command(mtd, ONENAND_CMD_RESET, 0, 0);
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this->command(mtd, ONENAND_CMD_RESET, 0, 0);
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this->wait(mtd, FL_RESETING);
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this->wait(mtd, FL_RESETTING);
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} else {
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} else {
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ops.mode = MTD_OPS_PLACE_OOB;
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ops.mode = MTD_OPS_PLACE_OOB;
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ops.ooblen = len;
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ops.ooblen = len;
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@ -3413,7 +3413,7 @@ static int flexonenand_get_boundary(struct mtd_info *mtd)
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this->boundary[die] = bdry & FLEXONENAND_PI_MASK;
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this->boundary[die] = bdry & FLEXONENAND_PI_MASK;
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this->command(mtd, ONENAND_CMD_RESET, 0, 0);
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this->command(mtd, ONENAND_CMD_RESET, 0, 0);
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this->wait(mtd, FL_RESETING);
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this->wait(mtd, FL_RESETTING);
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printk(KERN_INFO "Die %d boundary: %d%s\n", die,
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printk(KERN_INFO "Die %d boundary: %d%s\n", die,
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this->boundary[die], locked ? "(Locked)" : "(Unlocked)");
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this->boundary[die], locked ? "(Locked)" : "(Unlocked)");
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@ -3635,7 +3635,7 @@ static int flexonenand_set_boundary(struct mtd_info *mtd, int die,
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ret = this->wait(mtd, FL_WRITING);
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ret = this->wait(mtd, FL_WRITING);
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out:
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out:
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this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_REG_COMMAND);
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this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_REG_COMMAND);
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this->wait(mtd, FL_RESETING);
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this->wait(mtd, FL_RESETTING);
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if (!ret)
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if (!ret)
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/* Recalculate device size on boundary change*/
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/* Recalculate device size on boundary change*/
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flexonenand_get_size(mtd);
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flexonenand_get_size(mtd);
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@ -3671,7 +3671,7 @@ static int onenand_chip_probe(struct mtd_info *mtd)
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/* Reset OneNAND to read default register values */
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/* Reset OneNAND to read default register values */
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this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM);
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this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM);
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/* Wait reset */
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/* Wait reset */
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this->wait(mtd, FL_RESETING);
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this->wait(mtd, FL_RESETTING);
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/* Restore system configuration 1 */
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/* Restore system configuration 1 */
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this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);
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this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);
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@ -675,12 +675,12 @@ static int s5pc110_read_bufferram(struct mtd_info *mtd, int area,
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normal:
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normal:
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if (count != mtd->writesize) {
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if (count != mtd->writesize) {
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/* Copy the bufferram to memory to prevent unaligned access */
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/* Copy the bufferram to memory to prevent unaligned access */
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memcpy(this->page_buf, p, mtd->writesize);
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memcpy_fromio(this->page_buf, p, mtd->writesize);
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p = this->page_buf + offset;
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memcpy(buffer, this->page_buf + offset, count);
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} else {
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memcpy_fromio(buffer, p, count);
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}
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}
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memcpy(buffer, p, count);
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return 0;
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return 0;
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}
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}
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@ -914,8 +914,8 @@ static void cadence_nand_get_caps(struct cdns_nand_ctrl *cdns_ctrl)
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/* Prepare CDMA descriptor. */
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/* Prepare CDMA descriptor. */
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static void
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static void
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cadence_nand_cdma_desc_prepare(struct cdns_nand_ctrl *cdns_ctrl,
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cadence_nand_cdma_desc_prepare(struct cdns_nand_ctrl *cdns_ctrl,
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char nf_mem, u32 flash_ptr, char *mem_ptr,
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char nf_mem, u32 flash_ptr, dma_addr_t mem_ptr,
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char *ctrl_data_ptr, u16 ctype)
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dma_addr_t ctrl_data_ptr, u16 ctype)
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{
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{
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struct cadence_nand_cdma_desc *cdma_desc = cdns_ctrl->cdma_desc;
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struct cadence_nand_cdma_desc *cdma_desc = cdns_ctrl->cdma_desc;
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@ -931,13 +931,13 @@ cadence_nand_cdma_desc_prepare(struct cdns_nand_ctrl *cdns_ctrl,
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cdma_desc->command_flags |= CDMA_CF_DMA_MASTER;
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cdma_desc->command_flags |= CDMA_CF_DMA_MASTER;
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cdma_desc->command_flags |= CDMA_CF_INT;
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cdma_desc->command_flags |= CDMA_CF_INT;
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|
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cdma_desc->memory_pointer = (uintptr_t)mem_ptr;
|
cdma_desc->memory_pointer = mem_ptr;
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cdma_desc->status = 0;
|
cdma_desc->status = 0;
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cdma_desc->sync_flag_pointer = 0;
|
cdma_desc->sync_flag_pointer = 0;
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cdma_desc->sync_arguments = 0;
|
cdma_desc->sync_arguments = 0;
|
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|
|
||||||
cdma_desc->command_type = ctype;
|
cdma_desc->command_type = ctype;
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cdma_desc->ctrl_data_ptr = (uintptr_t)ctrl_data_ptr;
|
cdma_desc->ctrl_data_ptr = ctrl_data_ptr;
|
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}
|
}
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||||||
|
|
||||||
static u8 cadence_nand_check_desc_error(struct cdns_nand_ctrl *cdns_ctrl,
|
static u8 cadence_nand_check_desc_error(struct cdns_nand_ctrl *cdns_ctrl,
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||||||
|
@ -1280,8 +1280,7 @@ cadence_nand_cdma_transfer(struct cdns_nand_ctrl *cdns_ctrl, u8 chip_nr,
|
||||||
}
|
}
|
||||||
|
|
||||||
cadence_nand_cdma_desc_prepare(cdns_ctrl, chip_nr, page,
|
cadence_nand_cdma_desc_prepare(cdns_ctrl, chip_nr, page,
|
||||||
(void *)dma_buf, (void *)dma_ctrl_dat,
|
dma_buf, dma_ctrl_dat, ctype);
|
||||||
ctype);
|
|
||||||
|
|
||||||
status = cadence_nand_cdma_send_and_wait(cdns_ctrl, thread_nr);
|
status = cadence_nand_cdma_send_and_wait(cdns_ctrl, thread_nr);
|
||||||
|
|
||||||
|
@ -1360,7 +1359,7 @@ static int cadence_nand_erase(struct nand_chip *chip, u32 page)
|
||||||
|
|
||||||
cadence_nand_cdma_desc_prepare(cdns_ctrl,
|
cadence_nand_cdma_desc_prepare(cdns_ctrl,
|
||||||
cdns_chip->cs[chip->cur_cs],
|
cdns_chip->cs[chip->cur_cs],
|
||||||
page, NULL, NULL,
|
page, 0, 0,
|
||||||
CDMA_CT_ERASE);
|
CDMA_CT_ERASE);
|
||||||
status = cadence_nand_cdma_send_and_wait(cdns_ctrl, thread_nr);
|
status = cadence_nand_cdma_send_and_wait(cdns_ctrl, thread_nr);
|
||||||
if (status) {
|
if (status) {
|
||||||
|
|
|
@ -37,6 +37,7 @@
|
||||||
/* Max ECC buffer length */
|
/* Max ECC buffer length */
|
||||||
#define FMC2_MAX_ECC_BUF_LEN (FMC2_BCHDSRS_LEN * FMC2_MAX_SG)
|
#define FMC2_MAX_ECC_BUF_LEN (FMC2_BCHDSRS_LEN * FMC2_MAX_SG)
|
||||||
|
|
||||||
|
#define FMC2_TIMEOUT_US 1000
|
||||||
#define FMC2_TIMEOUT_MS 1000
|
#define FMC2_TIMEOUT_MS 1000
|
||||||
|
|
||||||
/* Timings */
|
/* Timings */
|
||||||
|
@ -53,6 +54,8 @@
|
||||||
#define FMC2_PMEM 0x88
|
#define FMC2_PMEM 0x88
|
||||||
#define FMC2_PATT 0x8c
|
#define FMC2_PATT 0x8c
|
||||||
#define FMC2_HECCR 0x94
|
#define FMC2_HECCR 0x94
|
||||||
|
#define FMC2_ISR 0x184
|
||||||
|
#define FMC2_ICR 0x188
|
||||||
#define FMC2_CSQCR 0x200
|
#define FMC2_CSQCR 0x200
|
||||||
#define FMC2_CSQCFGR1 0x204
|
#define FMC2_CSQCFGR1 0x204
|
||||||
#define FMC2_CSQCFGR2 0x208
|
#define FMC2_CSQCFGR2 0x208
|
||||||
|
@ -118,6 +121,12 @@
|
||||||
#define FMC2_PATT_ATTHIZ(x) (((x) & 0xff) << 24)
|
#define FMC2_PATT_ATTHIZ(x) (((x) & 0xff) << 24)
|
||||||
#define FMC2_PATT_DEFAULT 0x0a0a0a0a
|
#define FMC2_PATT_DEFAULT 0x0a0a0a0a
|
||||||
|
|
||||||
|
/* Register: FMC2_ISR */
|
||||||
|
#define FMC2_ISR_IHLF BIT(1)
|
||||||
|
|
||||||
|
/* Register: FMC2_ICR */
|
||||||
|
#define FMC2_ICR_CIHLF BIT(1)
|
||||||
|
|
||||||
/* Register: FMC2_CSQCR */
|
/* Register: FMC2_CSQCR */
|
||||||
#define FMC2_CSQCR_CSQSTART BIT(0)
|
#define FMC2_CSQCR_CSQSTART BIT(0)
|
||||||
|
|
||||||
|
@ -1322,6 +1331,31 @@ static void stm32_fmc2_write_data(struct nand_chip *chip, const void *buf,
|
||||||
stm32_fmc2_set_buswidth_16(fmc2, true);
|
stm32_fmc2_set_buswidth_16(fmc2, true);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int stm32_fmc2_waitrdy(struct nand_chip *chip, unsigned long timeout_ms)
|
||||||
|
{
|
||||||
|
struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
|
||||||
|
const struct nand_sdr_timings *timings;
|
||||||
|
u32 isr, sr;
|
||||||
|
|
||||||
|
/* Check if there is no pending requests to the NAND flash */
|
||||||
|
if (readl_relaxed_poll_timeout_atomic(fmc2->io_base + FMC2_SR, sr,
|
||||||
|
sr & FMC2_SR_NWRF, 1,
|
||||||
|
FMC2_TIMEOUT_US))
|
||||||
|
dev_warn(fmc2->dev, "Waitrdy timeout\n");
|
||||||
|
|
||||||
|
/* Wait tWB before R/B# signal is low */
|
||||||
|
timings = nand_get_sdr_timings(&chip->data_interface);
|
||||||
|
ndelay(PSEC_TO_NSEC(timings->tWB_max));
|
||||||
|
|
||||||
|
/* R/B# signal is low, clear high level flag */
|
||||||
|
writel_relaxed(FMC2_ICR_CIHLF, fmc2->io_base + FMC2_ICR);
|
||||||
|
|
||||||
|
/* Wait R/B# signal is high */
|
||||||
|
return readl_relaxed_poll_timeout_atomic(fmc2->io_base + FMC2_ISR,
|
||||||
|
isr, isr & FMC2_ISR_IHLF,
|
||||||
|
5, 1000 * timeout_ms);
|
||||||
|
}
|
||||||
|
|
||||||
static int stm32_fmc2_exec_op(struct nand_chip *chip,
|
static int stm32_fmc2_exec_op(struct nand_chip *chip,
|
||||||
const struct nand_operation *op,
|
const struct nand_operation *op,
|
||||||
bool check_only)
|
bool check_only)
|
||||||
|
@ -1366,8 +1400,8 @@ static int stm32_fmc2_exec_op(struct nand_chip *chip,
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case NAND_OP_WAITRDY_INSTR:
|
case NAND_OP_WAITRDY_INSTR:
|
||||||
ret = nand_soft_waitrdy(chip,
|
ret = stm32_fmc2_waitrdy(chip,
|
||||||
instr->ctx.waitrdy.timeout_ms);
|
instr->ctx.waitrdy.timeout_ms);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
@ -247,7 +247,8 @@ static int sm_read_sector(struct sm_ftl *ftl,
|
||||||
|
|
||||||
/* FTL can contain -1 entries that are by default filled with bits */
|
/* FTL can contain -1 entries that are by default filled with bits */
|
||||||
if (block == -1) {
|
if (block == -1) {
|
||||||
memset(buffer, 0xFF, SM_SECTOR_SIZE);
|
if (buffer)
|
||||||
|
memset(buffer, 0xFF, SM_SECTOR_SIZE);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -4596,6 +4596,7 @@ static void sst_set_default_init(struct spi_nor *nor)
|
||||||
static void st_micron_set_default_init(struct spi_nor *nor)
|
static void st_micron_set_default_init(struct spi_nor *nor)
|
||||||
{
|
{
|
||||||
nor->flags |= SNOR_F_HAS_LOCK;
|
nor->flags |= SNOR_F_HAS_LOCK;
|
||||||
|
nor->flags &= ~SNOR_F_HAS_16BIT_SR;
|
||||||
nor->params.quad_enable = NULL;
|
nor->params.quad_enable = NULL;
|
||||||
nor->params.set_4byte = st_micron_set_4byte;
|
nor->params.set_4byte = st_micron_set_4byte;
|
||||||
}
|
}
|
||||||
|
|
|
@ -40,7 +40,7 @@ typedef enum {
|
||||||
FL_READING,
|
FL_READING,
|
||||||
FL_CACHEDPRG,
|
FL_CACHEDPRG,
|
||||||
/* These 4 come from onenand_state_t, which has been unified here */
|
/* These 4 come from onenand_state_t, which has been unified here */
|
||||||
FL_RESETING,
|
FL_RESETTING,
|
||||||
FL_OTPING,
|
FL_OTPING,
|
||||||
FL_PREPARING_ERASE,
|
FL_PREPARING_ERASE,
|
||||||
FL_VERIFYING_ERASE,
|
FL_VERIFYING_ERASE,
|
||||||
|
|
Loading…
Reference in a new issue