regulator/mfd: Support ROHM BD71847 power management IC
BD71847 is reduced version of BD71837. DVS bucks 3 and 4 are removed as is LDO7. Voltage ranges of some regulators are expanded. Add initial support for BD71847 with BD71837 driver. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>hifive-unleashed-5.1
Matti Vaittinen
Mark Brown
parent
2e0fe4d0c6
commit
494edd266b
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@ -7,21 +7,16 @@
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// Datasheet available from
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// https://www.rohm.com/datasheet/BD71837MWV/bd71837mwv-e
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#include <linux/gpio_keys.h>
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#include <linux/i2c.h>
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#include <linux/input.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/rohm-bd718x7.h>
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#include <linux/mfd/core.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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/*
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* gpio_keys.h requires definiton of bool. It is brought in
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* by above includes. Keep this as last until gpio_keys.h gets fixed.
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*/
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#include <linux/gpio_keys.h>
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static const u8 supported_revisions[] = { 0xA2 /* BD71837 */ };
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#include <linux/types.h>
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static struct gpio_keys_button button = {
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.code = KEY_POWER,
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@ -41,8 +36,8 @@ static struct mfd_cell bd71837_mfd_cells[] = {
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.platform_data = &bd718xx_powerkey_data,
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.pdata_size = sizeof(bd718xx_powerkey_data),
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},
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{ .name = "bd71837-clk", },
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{ .name = "bd71837-pmic", },
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{ .name = "bd718xx-clk", },
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{ .name = "bd718xx-pmic", },
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};
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static const struct regmap_irq bd71837_irqs[] = {
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@ -61,16 +56,16 @@ static struct regmap_irq_chip bd71837_irq_chip = {
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.num_irqs = ARRAY_SIZE(bd71837_irqs),
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.num_regs = 1,
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.irq_reg_stride = 1,
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.status_base = BD71837_REG_IRQ,
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.mask_base = BD71837_REG_MIRQ,
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.ack_base = BD71837_REG_IRQ,
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.status_base = BD718XX_REG_IRQ,
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.mask_base = BD718XX_REG_MIRQ,
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.ack_base = BD718XX_REG_IRQ,
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.init_ack_masked = true,
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.mask_invert = false,
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};
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static const struct regmap_range pmic_status_range = {
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.range_min = BD71837_REG_IRQ,
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.range_max = BD71837_REG_POW_STATE,
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.range_min = BD718XX_REG_IRQ,
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.range_max = BD718XX_REG_POW_STATE,
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};
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static const struct regmap_access_table volatile_regs = {
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@ -82,7 +77,7 @@ static const struct regmap_config bd71837_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.volatile_table = &volatile_regs,
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.max_register = BD71837_MAX_REGISTER - 1,
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.max_register = BD718XX_MAX_REGISTER - 1,
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.cache_type = REGCACHE_RBTREE,
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};
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@ -90,8 +85,12 @@ static int bd71837_i2c_probe(struct i2c_client *i2c,
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const struct i2c_device_id *id)
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{
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struct bd71837 *bd71837;
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int ret, i;
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unsigned int val;
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int ret;
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if (!i2c->irq) {
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dev_err(&i2c->dev, "No IRQ configured\n");
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return -EINVAL;
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}
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bd71837 = devm_kzalloc(&i2c->dev, sizeof(struct bd71837), GFP_KERNEL);
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@ -99,12 +98,8 @@ static int bd71837_i2c_probe(struct i2c_client *i2c,
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return -ENOMEM;
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bd71837->chip_irq = i2c->irq;
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if (!bd71837->chip_irq) {
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dev_err(&i2c->dev, "No IRQ configured\n");
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return -EINVAL;
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}
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bd71837->chip_type = (unsigned int)(uintptr_t)
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of_device_get_match_data(&i2c->dev);
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bd71837->dev = &i2c->dev;
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dev_set_drvdata(&i2c->dev, bd71837);
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@ -114,20 +109,6 @@ static int bd71837_i2c_probe(struct i2c_client *i2c,
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return PTR_ERR(bd71837->regmap);
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}
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ret = regmap_read(bd71837->regmap, BD71837_REG_REV, &val);
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if (ret) {
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dev_err(&i2c->dev, "Read BD71837_REG_DEVICE failed\n");
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return ret;
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}
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for (i = 0; i < ARRAY_SIZE(supported_revisions); i++)
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if (supported_revisions[i] == val)
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break;
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if (i == ARRAY_SIZE(supported_revisions)) {
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dev_err(&i2c->dev, "Unsupported chip revision\n");
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return -ENODEV;
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}
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ret = devm_regmap_add_irq_chip(&i2c->dev, bd71837->regmap,
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bd71837->chip_irq, IRQF_ONESHOT, 0,
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&bd71837_irq_chip, &bd71837->irq_data);
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@ -138,7 +119,7 @@ static int bd71837_i2c_probe(struct i2c_client *i2c,
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/* Configure short press to 10 milliseconds */
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ret = regmap_update_bits(bd71837->regmap,
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BD71837_REG_PWRONCONFIG0,
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BD718XX_REG_PWRONCONFIG0,
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BD718XX_PWRBTN_PRESS_DURATION_MASK,
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BD718XX_PWRBTN_SHORT_PRESS_10MS);
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if (ret) {
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@ -149,7 +130,7 @@ static int bd71837_i2c_probe(struct i2c_client *i2c,
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/* Configure long press to 10 seconds */
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ret = regmap_update_bits(bd71837->regmap,
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BD71837_REG_PWRONCONFIG1,
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BD718XX_REG_PWRONCONFIG1,
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BD718XX_PWRBTN_PRESS_DURATION_MASK,
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BD718XX_PWRBTN_LONG_PRESS_10S);
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@ -179,7 +160,14 @@ static int bd71837_i2c_probe(struct i2c_client *i2c,
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}
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static const struct of_device_id bd71837_of_match[] = {
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{ .compatible = "rohm,bd71837", },
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{
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.compatible = "rohm,bd71837",
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.data = (void *)BD718XX_TYPE_BD71837,
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},
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{
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.compatible = "rohm,bd71847",
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.data = (void *)BD718XX_TYPE_BD71847,
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},
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{ }
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};
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MODULE_DEVICE_TABLE(of, bd71837_of_match);
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File diff suppressed because it is too large
Load Diff
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@ -7,106 +7,125 @@
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#include <linux/regmap.h>
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enum {
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BD71837_BUCK1 = 0,
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BD71837_BUCK2,
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BD71837_BUCK3,
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BD71837_BUCK4,
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BD71837_BUCK5,
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BD71837_BUCK6,
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BD71837_BUCK7,
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BD71837_BUCK8,
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BD71837_LDO1,
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BD71837_LDO2,
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BD71837_LDO3,
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BD71837_LDO4,
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BD71837_LDO5,
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BD71837_LDO6,
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BD71837_LDO7,
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BD71837_REGULATOR_CNT,
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BD718XX_TYPE_BD71837 = 0,
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BD718XX_TYPE_BD71847,
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BD718XX_TYPE_AMOUNT
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};
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#define BD71837_BUCK1_VOLTAGE_NUM 0x40
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#define BD71837_BUCK2_VOLTAGE_NUM 0x40
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#define BD71837_BUCK3_VOLTAGE_NUM 0x40
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#define BD71837_BUCK4_VOLTAGE_NUM 0x40
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enum {
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BD718XX_BUCK1 = 0,
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BD718XX_BUCK2,
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BD718XX_BUCK3,
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BD718XX_BUCK4,
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BD718XX_BUCK5,
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BD718XX_BUCK6,
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BD718XX_BUCK7,
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BD718XX_BUCK8,
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BD718XX_LDO1,
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BD718XX_LDO2,
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BD718XX_LDO3,
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BD718XX_LDO4,
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BD718XX_LDO5,
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BD718XX_LDO6,
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BD718XX_LDO7,
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BD718XX_REGULATOR_AMOUNT,
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};
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#define BD71837_BUCK5_VOLTAGE_NUM 0x08
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/* Common voltage configurations
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*
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* Note, we support only one range of voltages for each buck/LDO until we
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* get pickable ranges support. (See range selection bits for BUCK5 and
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* LDO1. On BD71847 also the second no DVS buck and LDO5)
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*/
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#define BD718XX_DVS_BUCK_VOLTAGE_NUM 0x3D
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#define BD718XX_1ST_NODVS_BUCK_VOLTAGE_NUM 0x08
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#define BD71837_4TH_NODVS_BUCK_VOLTAGE_NUM 0x3D
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#define BD718XX_LDO1_VOLTAGE_NUM 0x04
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#define BD718XX_LDO2_VOLTAGE_NUM 0x02
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#define BD718XX_LDO3_VOLTAGE_NUM 0x10
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#define BD718XX_LDO4_VOLTAGE_NUM 0x0A
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#define BD718XX_LDO5_VOLTAGE_NUM 0x10
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#define BD718XX_LDO6_VOLTAGE_NUM 0x0A
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/* BD71837 specific voltage configurations */
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#define BD71837_BUCK6_VOLTAGE_NUM 0x04
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#define BD71837_BUCK7_VOLTAGE_NUM 0x08
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#define BD71837_BUCK8_VOLTAGE_NUM 0x40
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#define BD71837_LDO1_VOLTAGE_NUM 0x04
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#define BD71837_LDO2_VOLTAGE_NUM 0x02
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#define BD71837_LDO3_VOLTAGE_NUM 0x10
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#define BD71837_LDO4_VOLTAGE_NUM 0x10
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#define BD71837_LDO5_VOLTAGE_NUM 0x10
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#define BD71837_LDO6_VOLTAGE_NUM 0x10
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#define BD71837_LDO7_VOLTAGE_NUM 0x10
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/* BD71847 specific voltage configurations */
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#define BD71847_BUCK4_VOLTAGE_NUM 0x04
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/* Registers specific to BD71837 */
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enum {
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BD71837_REG_REV = 0x00,
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BD71837_REG_SWRESET = 0x01,
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BD71837_REG_I2C_DEV = 0x02,
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BD71837_REG_PWRCTRL0 = 0x03,
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BD71837_REG_PWRCTRL1 = 0x04,
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BD71837_REG_BUCK1_CTRL = 0x05,
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BD71837_REG_BUCK2_CTRL = 0x06,
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BD71837_REG_BUCK3_CTRL = 0x07,
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BD71837_REG_BUCK4_CTRL = 0x08,
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BD71837_REG_BUCK5_CTRL = 0x09,
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BD71837_REG_BUCK6_CTRL = 0x0A,
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BD71837_REG_BUCK7_CTRL = 0x0B,
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BD71837_REG_BUCK8_CTRL = 0x0C,
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BD71837_REG_BUCK1_VOLT_RUN = 0x0D,
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BD71837_REG_BUCK1_VOLT_IDLE = 0x0E,
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BD71837_REG_BUCK1_VOLT_SUSP = 0x0F,
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BD71837_REG_BUCK2_VOLT_RUN = 0x10,
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BD71837_REG_BUCK2_VOLT_IDLE = 0x11,
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BD71837_REG_BUCK3_VOLT_RUN = 0x12,
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BD71837_REG_BUCK4_VOLT_RUN = 0x13,
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BD71837_REG_BUCK5_VOLT = 0x14,
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BD71837_REG_BUCK6_VOLT = 0x15,
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BD71837_REG_BUCK7_VOLT = 0x16,
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BD71837_REG_BUCK8_VOLT = 0x17,
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BD71837_REG_LDO1_VOLT = 0x18,
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BD71837_REG_LDO2_VOLT = 0x19,
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BD71837_REG_LDO3_VOLT = 0x1A,
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BD71837_REG_LDO4_VOLT = 0x1B,
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BD71837_REG_LDO5_VOLT = 0x1C,
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BD71837_REG_LDO6_VOLT = 0x1D,
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BD71837_REG_LDO7_VOLT = 0x1E,
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BD71837_REG_TRANS_COND0 = 0x1F,
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BD71837_REG_TRANS_COND1 = 0x20,
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BD71837_REG_VRFAULTEN = 0x21,
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BD718XX_REG_MVRFLTMASK0 = 0x22,
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BD718XX_REG_MVRFLTMASK1 = 0x23,
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BD718XX_REG_MVRFLTMASK2 = 0x24,
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BD71837_REG_RCVCFG = 0x25,
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BD71837_REG_RCVNUM = 0x26,
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BD71837_REG_PWRONCONFIG0 = 0x27,
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BD71837_REG_PWRONCONFIG1 = 0x28,
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BD71837_REG_RESETSRC = 0x29,
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BD71837_REG_MIRQ = 0x2A,
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BD71837_REG_IRQ = 0x2B,
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BD71837_REG_IN_MON = 0x2C,
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BD71837_REG_POW_STATE = 0x2D,
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BD71837_REG_OUT32K = 0x2E,
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BD71837_REG_REGLOCK = 0x2F,
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BD71837_REG_OTPVER = 0xFF,
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BD71837_MAX_REGISTER = 0x100,
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BD71837_REG_BUCK3_CTRL = 0x07,
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BD71837_REG_BUCK4_CTRL = 0x08,
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BD71837_REG_BUCK3_VOLT_RUN = 0x12,
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BD71837_REG_BUCK4_VOLT_RUN = 0x13,
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BD71837_REG_LDO7_VOLT = 0x1E,
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};
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/* Registers common for BD71837 and BD71847 */
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enum {
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BD718XX_REG_REV = 0x00,
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BD718XX_REG_SWRESET = 0x01,
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BD718XX_REG_I2C_DEV = 0x02,
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BD718XX_REG_PWRCTRL0 = 0x03,
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BD718XX_REG_PWRCTRL1 = 0x04,
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BD718XX_REG_BUCK1_CTRL = 0x05,
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BD718XX_REG_BUCK2_CTRL = 0x06,
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BD718XX_REG_1ST_NODVS_BUCK_CTRL = 0x09,
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BD718XX_REG_2ND_NODVS_BUCK_CTRL = 0x0A,
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BD718XX_REG_3RD_NODVS_BUCK_CTRL = 0x0B,
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BD718XX_REG_4TH_NODVS_BUCK_CTRL = 0x0C,
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BD718XX_REG_BUCK1_VOLT_RUN = 0x0D,
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BD718XX_REG_BUCK1_VOLT_IDLE = 0x0E,
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BD718XX_REG_BUCK1_VOLT_SUSP = 0x0F,
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BD718XX_REG_BUCK2_VOLT_RUN = 0x10,
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BD718XX_REG_BUCK2_VOLT_IDLE = 0x11,
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BD718XX_REG_1ST_NODVS_BUCK_VOLT = 0x14,
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BD718XX_REG_2ND_NODVS_BUCK_VOLT = 0x15,
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BD718XX_REG_3RD_NODVS_BUCK_VOLT = 0x16,
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BD718XX_REG_4TH_NODVS_BUCK_VOLT = 0x17,
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BD718XX_REG_LDO1_VOLT = 0x18,
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BD718XX_REG_LDO2_VOLT = 0x19,
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BD718XX_REG_LDO3_VOLT = 0x1A,
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BD718XX_REG_LDO4_VOLT = 0x1B,
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BD718XX_REG_LDO5_VOLT = 0x1C,
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BD718XX_REG_LDO6_VOLT = 0x1D,
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BD718XX_REG_TRANS_COND0 = 0x1F,
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BD718XX_REG_TRANS_COND1 = 0x20,
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BD718XX_REG_VRFAULTEN = 0x21,
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BD718XX_REG_MVRFLTMASK0 = 0x22,
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BD718XX_REG_MVRFLTMASK1 = 0x23,
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BD718XX_REG_MVRFLTMASK2 = 0x24,
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BD718XX_REG_RCVCFG = 0x25,
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BD718XX_REG_RCVNUM = 0x26,
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BD718XX_REG_PWRONCONFIG0 = 0x27,
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BD718XX_REG_PWRONCONFIG1 = 0x28,
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BD718XX_REG_RESETSRC = 0x29,
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BD718XX_REG_MIRQ = 0x2A,
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BD718XX_REG_IRQ = 0x2B,
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BD718XX_REG_IN_MON = 0x2C,
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BD718XX_REG_POW_STATE = 0x2D,
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BD718XX_REG_OUT32K = 0x2E,
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BD718XX_REG_REGLOCK = 0x2F,
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BD718XX_REG_OTPVER = 0xFF,
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BD718XX_MAX_REGISTER = 0x100,
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};
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#define REGLOCK_PWRSEQ 0x1
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#define REGLOCK_VREG 0x10
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/* Generic BUCK control masks */
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#define BD71837_BUCK_SEL 0x02
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#define BD71837_BUCK_EN 0x01
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#define BD71837_BUCK_RUN_ON 0x04
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#define BD718XX_BUCK_SEL 0x02
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#define BD718XX_BUCK_EN 0x01
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#define BD718XX_BUCK_RUN_ON 0x04
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/* Generic LDO masks */
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#define BD71837_LDO_SEL 0x80
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#define BD71837_LDO_EN 0x40
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#define BD718XX_LDO_SEL 0x80
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#define BD718XX_LDO_EN 0x40
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/* BD71837 BUCK ramp rate CTRL reg bits */
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#define BUCK_RAMPRATE_MASK 0xC0
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@ -115,49 +134,27 @@ enum {
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#define BUCK_RAMPRATE_2P50MV 0x2
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#define BUCK_RAMPRATE_1P25MV 0x3
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/* BD71837_REG_BUCK1_VOLT_RUN bits */
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#define BUCK1_RUN_MASK 0x3F
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#define BUCK1_RUN_DEFAULT 0x14
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#define DVS_BUCK_RUN_MASK 0x3F
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#define DVS_BUCK_SUSP_MASK 0x3F
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#define DVS_BUCK_IDLE_MASK 0x3F
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/* BD71837_REG_BUCK1_VOLT_SUSP bits */
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#define BUCK1_SUSP_MASK 0x3F
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#define BUCK1_SUSP_DEFAULT 0x14
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#define BD718XX_1ST_NODVS_BUCK_MASK 0x07
|
||||
#define BD71847_BUCK4_MASK 0x03
|
||||
#define BD71837_BUCK6_MASK 0x03
|
||||
#define BD718XX_3RD_NODVS_BUCK_MASK 0x07
|
||||
#define BD718XX_4TH_NODVS_BUCK_MASK 0x3F
|
||||
|
||||
/* BD71837_REG_BUCK1_VOLT_IDLE bits */
|
||||
#define BUCK1_IDLE_MASK 0x3F
|
||||
#define BUCK1_IDLE_DEFAULT 0x14
|
||||
#define BD718XX_LDO1_MASK 0x03
|
||||
#define BD718XX_LDO2_MASK 0x20
|
||||
#define BD718XX_LDO3_MASK 0x0F
|
||||
#define BD718XX_LDO4_MASK 0x0F
|
||||
#define BD718XX_LDO6_MASK 0x0F
|
||||
|
||||
/* BD71837_REG_BUCK2_VOLT_RUN bits */
|
||||
#define BUCK2_RUN_MASK 0x3F
|
||||
#define BUCK2_RUN_DEFAULT 0x1E
|
||||
#define BD71837_LDO5_MASK 0x0F
|
||||
#define BD71847_LDO5_MASK 0x0F
|
||||
|
||||
/* BD71837_REG_BUCK2_VOLT_IDLE bits */
|
||||
#define BUCK2_IDLE_MASK 0x3F
|
||||
#define BUCK2_IDLE_DEFAULT 0x14
|
||||
#define BD71837_LDO7_MASK 0x0F
|
||||
|
||||
/* BD71837_REG_BUCK3_VOLT_RUN bits */
|
||||
#define BUCK3_RUN_MASK 0x3F
|
||||
#define BUCK3_RUN_DEFAULT 0x1E
|
||||
|
||||
/* BD71837_REG_BUCK4_VOLT_RUN bits */
|
||||
#define BUCK4_RUN_MASK 0x3F
|
||||
#define BUCK4_RUN_DEFAULT 0x1E
|
||||
|
||||
/* BD71837_REG_BUCK5_VOLT bits */
|
||||
#define BUCK5_MASK 0x07
|
||||
#define BUCK5_DEFAULT 0x02
|
||||
|
||||
/* BD71837_REG_BUCK6_VOLT bits */
|
||||
#define BUCK6_MASK 0x03
|
||||
#define BUCK6_DEFAULT 0x03
|
||||
|
||||
/* BD71837_REG_BUCK7_VOLT bits */
|
||||
#define BUCK7_MASK 0x07
|
||||
#define BUCK7_DEFAULT 0x03
|
||||
|
||||
/* BD71837_REG_BUCK8_VOLT bits */
|
||||
#define BUCK8_MASK 0x3F
|
||||
#define BUCK8_DEFAULT 0x1E
|
||||
|
||||
/* BD718XX Voltage monitoring masks */
|
||||
#define BD718XX_BUCK1_VRMON80 0x1
|
||||
|
|
@ -221,27 +218,6 @@ enum {
|
|||
#define BD71837_INT_ON_REQ_MASK 0x2
|
||||
#define BD71837_INT_STBY_REQ_MASK 0x1
|
||||
|
||||
/* BD71837_REG_LDO1_VOLT bits */
|
||||
#define LDO1_MASK 0x03
|
||||
|
||||
/* BD71837_REG_LDO1_VOLT bits */
|
||||
#define LDO2_MASK 0x20
|
||||
|
||||
/* BD71837_REG_LDO3_VOLT bits */
|
||||
#define LDO3_MASK 0x0F
|
||||
|
||||
/* BD71837_REG_LDO4_VOLT bits */
|
||||
#define LDO4_MASK 0x0F
|
||||
|
||||
/* BD71837_REG_LDO5_VOLT bits */
|
||||
#define LDO5_MASK 0x0F
|
||||
|
||||
/* BD71837_REG_LDO6_VOLT bits */
|
||||
#define LDO6_MASK 0x0F
|
||||
|
||||
/* BD71837_REG_LDO7_VOLT bits */
|
||||
#define LDO7_MASK 0x0F
|
||||
|
||||
/* Register write induced reset settings */
|
||||
|
||||
/*
|
||||
|
|
@ -341,10 +317,11 @@ enum {
|
|||
BD718XX_PWRBTN_LONG_PRESS_15S
|
||||
};
|
||||
|
||||
struct bd71837_pmic;
|
||||
struct bd71837_clk;
|
||||
struct bd718xx_pmic;
|
||||
struct bd718xx_clk;
|
||||
|
||||
struct bd71837 {
|
||||
unsigned int chip_type;
|
||||
struct device *dev;
|
||||
struct regmap *regmap;
|
||||
unsigned long int id;
|
||||
|
|
@ -352,8 +329,8 @@ struct bd71837 {
|
|||
int chip_irq;
|
||||
struct regmap_irq_chip_data *irq_data;
|
||||
|
||||
struct bd71837_pmic *pmic;
|
||||
struct bd71837_clk *clk;
|
||||
struct bd718xx_pmic *pmic;
|
||||
struct bd718xx_clk *clk;
|
||||
};
|
||||
|
||||
#endif /* __LINUX_MFD_BD71837_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue