gpio-sifive: support GPIO on SiFive SoCs
Wesley W. Terpstra
Alistair Francis
parent
5088d93018
commit
49580344e3
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@ -0,0 +1,28 @@
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SiFive GPIO controller bindings
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Required properties:
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- compatible:
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- "sifive,gpio0"
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- reg: Physical base address and length of the controller's registers.
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- #gpio-cells : Should be 2
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- The first cell is the gpio offset number.
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- The second cell indicates the polarity of the GPIO
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- gpio-controller : Marks the device node as a GPIO controller.
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- interrupt-controller: Mark the device node as an interrupt controller
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- #interrupt-cells : Should be 2.
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- The first cell is the GPIO offset number within the GPIO controller.
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- The second cell is the edge/level to use for interrupt generation.
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- interrupts: Specify the interrupts, one per GPIO
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Example:
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gpio: gpio@10060000 {
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compatible = "sifive,gpio0";
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interrupt-parent = <&plic>;
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interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>;
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reg = <0x0 0x10060000 0x0 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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@ -451,6 +451,13 @@ config GPIO_SAMA5D2_PIOBU
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The difference from regular GPIOs is that they
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maintain their value during backup/self-refresh.
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config GPIO_SIFIVE
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bool "SiFive GPIO support"
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depends on OF_GPIO
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select GPIOLIB_IRQCHIP
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help
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Say yes here to support the GPIO device on SiFive SoCs.
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config GPIO_SIOX
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tristate "SIOX GPIO support"
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depends on SIOX
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@ -114,6 +114,7 @@ obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o
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obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) += gpio-sama5d2-piobu.o
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obj-$(CONFIG_GPIO_SCH) += gpio-sch.o
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obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o
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obj-$(CONFIG_GPIO_SIFIVE) += gpio-sifive.o
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obj-$(CONFIG_GPIO_SNPS_CREG) += gpio-creg-snps.o
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obj-$(CONFIG_GPIO_SODAVILLE) += gpio-sodaville.o
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obj-$(CONFIG_GPIO_SPEAR_SPICS) += gpio-spear-spics.o
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@ -0,0 +1,322 @@
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/*
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* SiFive GPIO driver
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*
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* Copyright (C) 2018 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/of_irq.h>
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#include <linux/gpio/driver.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#define GPIO_INPUT_VAL 0x00
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#define GPIO_INPUT_EN 0x04
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#define GPIO_OUTPUT_EN 0x08
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#define GPIO_OUTPUT_VAL 0x0C
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#define GPIO_RISE_IE 0x18
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#define GPIO_RISE_IP 0x1C
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#define GPIO_FALL_IE 0x20
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#define GPIO_FALL_IP 0x24
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#define GPIO_HIGH_IE 0x28
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#define GPIO_HIGH_IP 0x2C
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#define GPIO_LOW_IE 0x30
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#define GPIO_LOW_IP 0x34
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#define GPIO_OUTPUT_XOR 0x40
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#define MAX_GPIO 32
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struct sifive_gpio {
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raw_spinlock_t lock;
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void __iomem *base;
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struct gpio_chip gc;
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unsigned long enabled;
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unsigned trigger[MAX_GPIO];
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unsigned int irq_parent[MAX_GPIO];
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struct sifive_gpio *self_ptr[MAX_GPIO];
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};
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static void sifive_assign_bit(void __iomem *ptr, int offset, int value)
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{
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// It's frustrating that we are not allowed to use the device atomics
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// which are GUARANTEED to be supported by this device on RISC-V
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u32 bit = BIT(offset), old = ioread32(ptr);
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if (value)
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iowrite32(old | bit, ptr);
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else
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iowrite32(old & ~bit, ptr);
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}
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static int sifive_direction_input(struct gpio_chip *gc, unsigned offset)
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{
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struct sifive_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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if (offset >= gc->ngpio)
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return -EINVAL;
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raw_spin_lock_irqsave(&chip->lock, flags);
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sifive_assign_bit(chip->base + GPIO_OUTPUT_EN, offset, 0);
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sifive_assign_bit(chip->base + GPIO_INPUT_EN, offset, 1);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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static int sifive_direction_output(struct gpio_chip *gc, unsigned offset, int value)
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{
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struct sifive_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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if (offset >= gc->ngpio)
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return -EINVAL;
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raw_spin_lock_irqsave(&chip->lock, flags);
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sifive_assign_bit(chip->base + GPIO_INPUT_EN, offset, 0);
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sifive_assign_bit(chip->base + GPIO_OUTPUT_VAL, offset, value);
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sifive_assign_bit(chip->base + GPIO_OUTPUT_EN, offset, 1);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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static int sifive_get_direction(struct gpio_chip *gc, unsigned offset)
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{
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struct sifive_gpio *chip = gpiochip_get_data(gc);
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if (offset >= gc->ngpio)
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return -EINVAL;
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return !(ioread32(chip->base + GPIO_OUTPUT_EN) & BIT(offset));
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}
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static int sifive_get_value(struct gpio_chip *gc, unsigned offset)
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{
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struct sifive_gpio *chip = gpiochip_get_data(gc);
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if (offset >= gc->ngpio)
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return -EINVAL;
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return !!(ioread32(chip->base + GPIO_INPUT_VAL) & BIT(offset));
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}
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static void sifive_set_value(struct gpio_chip *gc, unsigned offset, int value)
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{
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struct sifive_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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if (offset >= gc->ngpio)
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return;
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raw_spin_lock_irqsave(&chip->lock, flags);
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sifive_assign_bit(chip->base + GPIO_OUTPUT_VAL, offset, value);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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}
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static void sifive_set_ie(struct sifive_gpio *chip, int offset)
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{
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unsigned long flags;
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unsigned trigger;
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raw_spin_lock_irqsave(&chip->lock, flags);
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trigger = (chip->enabled & BIT(offset)) ? chip->trigger[offset] : 0;
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sifive_assign_bit(chip->base + GPIO_RISE_IE, offset, trigger & IRQ_TYPE_EDGE_RISING);
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sifive_assign_bit(chip->base + GPIO_FALL_IE, offset, trigger & IRQ_TYPE_EDGE_FALLING);
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sifive_assign_bit(chip->base + GPIO_HIGH_IE, offset, trigger & IRQ_TYPE_LEVEL_HIGH);
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sifive_assign_bit(chip->base + GPIO_LOW_IE, offset, trigger & IRQ_TYPE_LEVEL_LOW);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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}
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static int sifive_irq_set_type(struct irq_data *d, unsigned trigger)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct sifive_gpio *chip = gpiochip_get_data(gc);
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int offset = irqd_to_hwirq(d);
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if (offset < 0 || offset >= gc->ngpio)
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return -EINVAL;
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chip->trigger[offset] = trigger;
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sifive_set_ie(chip, offset);
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return 0;
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}
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/* chained_irq_{enter,exit} already mask the parent */
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static void sifive_irq_mask(struct irq_data *d) { }
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static void sifive_irq_unmask(struct irq_data *d) { }
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static void sifive_irq_enable(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct sifive_gpio *chip = gpiochip_get_data(gc);
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int offset = irqd_to_hwirq(d) % MAX_GPIO; // must not fail
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u32 bit = BIT(offset);
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/* Switch to input */
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sifive_direction_input(gc, offset);
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/* Clear any sticky pending interrupts */
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iowrite32(bit, chip->base + GPIO_RISE_IP);
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iowrite32(bit, chip->base + GPIO_FALL_IP);
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iowrite32(bit, chip->base + GPIO_HIGH_IP);
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iowrite32(bit, chip->base + GPIO_LOW_IP);
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/* Enable interrupts */
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assign_bit(offset, &chip->enabled, 1);
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sifive_set_ie(chip, offset);
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}
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static void sifive_irq_disable(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct sifive_gpio *chip = gpiochip_get_data(gc);
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int offset = irqd_to_hwirq(d) % MAX_GPIO; // must not fail
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assign_bit(offset, &chip->enabled, 0);
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sifive_set_ie(chip, offset);
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}
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static struct irq_chip sifive_irqchip = {
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.name = "sifive-gpio",
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.irq_set_type = sifive_irq_set_type,
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.irq_mask = sifive_irq_mask,
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.irq_unmask = sifive_irq_unmask,
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.irq_enable = sifive_irq_enable,
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.irq_disable = sifive_irq_disable,
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};
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static void sifive_irq_handler(struct irq_desc *desc)
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{
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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struct sifive_gpio **self_ptr = irq_desc_get_handler_data(desc);
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struct sifive_gpio *chip = *self_ptr;
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int offset = self_ptr - &chip->self_ptr[0];
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u32 bit = BIT(offset);
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chained_irq_enter(irqchip, desc);
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/* Re-arm the edge triggers so don't miss the next one */
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iowrite32(bit, chip->base + GPIO_RISE_IP);
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iowrite32(bit, chip->base + GPIO_FALL_IP);
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generic_handle_irq(irq_find_mapping(chip->gc.irq.domain, offset));
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/* Re-arm the level triggers after handling to prevent spurious refire */
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iowrite32(bit, chip->base + GPIO_HIGH_IP);
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iowrite32(bit, chip->base + GPIO_LOW_IP);
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chained_irq_exit(irqchip, desc);
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}
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static int sifive_gpio_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *node = pdev->dev.of_node;
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struct sifive_gpio *chip;
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struct resource *res;
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int gpio, irq, ret, ngpio;
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chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
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if (!chip) {
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dev_err(dev, "out of memory\n");
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return -ENOMEM;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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chip->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(chip->base)) {
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dev_err(dev, "failed to allocate device memory\n");
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return PTR_ERR(chip->base);
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}
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ngpio = of_irq_count(node);
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if (ngpio >= MAX_GPIO) {
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dev_err(dev, "too many interrupts\n");
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return -EINVAL;
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}
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raw_spin_lock_init(&chip->lock);
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chip->gc.direction_input = sifive_direction_input;
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chip->gc.direction_output = sifive_direction_output;
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chip->gc.get_direction = sifive_get_direction;
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chip->gc.get = sifive_get_value;
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chip->gc.set = sifive_set_value;
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chip->gc.base = -1;
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chip->gc.ngpio = ngpio;
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chip->gc.label = dev_name(dev);
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chip->gc.parent = dev;
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chip->gc.owner = THIS_MODULE;
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ret = gpiochip_add_data(&chip->gc, chip);
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if (ret)
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return ret;
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/* Disable all GPIO interrupts before enabling parent interrupts */
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iowrite32(0, chip->base + GPIO_RISE_IE);
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iowrite32(0, chip->base + GPIO_FALL_IE);
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iowrite32(0, chip->base + GPIO_HIGH_IE);
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iowrite32(0, chip->base + GPIO_LOW_IE);
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chip->enabled = 0;
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ret = gpiochip_irqchip_add(&chip->gc, &sifive_irqchip, 0, handle_simple_irq, IRQ_TYPE_NONE);
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if (ret) {
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dev_err(dev, "could not add irqchip\n");
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gpiochip_remove(&chip->gc);
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return ret;
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}
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chip->gc.irq.num_parents = ngpio;
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chip->gc.irq.parents = &chip->irq_parent[0];
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chip->gc.irq.map = &chip->irq_parent[0];
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for (gpio = 0; gpio < ngpio; ++gpio) {
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irq = platform_get_irq(pdev, gpio);
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if (irq < 0) {
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dev_err(dev, "invalid IRQ\n");
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gpiochip_remove(&chip->gc);
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return -ENODEV;
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}
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chip->irq_parent[gpio] = irq;
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chip->self_ptr[gpio] = chip;
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chip->trigger[gpio] = IRQ_TYPE_LEVEL_HIGH;
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}
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for (gpio = 0; gpio < ngpio; ++gpio) {
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irq = chip->irq_parent[gpio];
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irq_set_chained_handler_and_data(irq, sifive_irq_handler, &chip->self_ptr[gpio]);
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irq_set_parent(irq_find_mapping(chip->gc.irq.domain, gpio), irq);
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}
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platform_set_drvdata(pdev, chip);
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dev_info(dev, "SiFive GPIO chip registered %d GPIOs\n", ngpio);
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return 0;
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}
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static const struct of_device_id sifive_gpio_match[] = {
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{
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.compatible = "sifive,gpio0",
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},
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{ },
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};
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static struct platform_driver sifive_gpio_driver = {
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.probe = sifive_gpio_probe,
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.driver = {
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.name = "sifive_gpio",
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.of_match_table = of_match_ptr(sifive_gpio_match),
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},
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};
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builtin_platform_driver(sifive_gpio_driver)
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