net: Add MDIO bus driver for the Hisilicon FEMAC
This patch adds a separate driver for the MDIO interface of the Hisilicon Fast Ethernet MAC. Signed-off-by: Dongpo Li <lidongpo@hisilicon.com> Reviewed-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>hifive-unleashed-5.1
Dongpo Li
David S. Miller
parent
8d8836d4dc
commit
4960e4b1e6
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@ -0,0 +1,22 @@
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Hisilicon Fast Ethernet MDIO Controller interface
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Required properties:
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- compatible: should be "hisilicon,hisi-femac-mdio".
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- reg: address and length of the register set for the device.
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- clocks: A phandle to the reference clock for this device.
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- PHY subnode: inherits from phy binding [1]
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[1] Documentation/devicetree/bindings/net/phy.txt
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Example:
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mdio: mdio@10091100 {
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compatible = "hisilicon,hisi-femac-mdio";
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reg = <0x10091100 0x10>;
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clocks = <&crg HI3516CV300_MDIO_CLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: phy@1 {
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reg = <1>;
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};
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};
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@ -294,6 +294,13 @@ config INTEL_XWAY_PHY
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PEF 7061, PEF 7071 and PEF 7072 or integrated into the Intel
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SoCs xRX200, xRX300, xRX330, xRX350 and xRX550.
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config MDIO_HISI_FEMAC
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tristate "Hisilicon FEMAC MDIO bus controller"
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depends on HAS_IOMEM && OF_MDIO
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help
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This module provides a driver for the MDIO busses found in the
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Hisilicon SoC that have an Fast Ethernet MAC.
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endif # PHYLIB
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config MICREL_KS8995MA
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@ -47,3 +47,4 @@ obj-$(CONFIG_MDIO_BCM_UNIMAC) += mdio-bcm-unimac.o
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obj-$(CONFIG_MICROCHIP_PHY) += microchip.o
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obj-$(CONFIG_MDIO_BCM_IPROC) += mdio-bcm-iproc.o
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obj-$(CONFIG_INTEL_XWAY_PHY) += intel-xway.o
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obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o
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@ -0,0 +1,166 @@
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/*
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* Hisilicon Fast Ethernet MDIO Bus Driver
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*
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* Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_mdio.h>
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#include <linux/platform_device.h>
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#define MDIO_RWCTRL 0x00
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#define MDIO_RO_DATA 0x04
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#define MDIO_WRITE BIT(13)
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#define MDIO_RW_FINISH BIT(15)
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#define BIT_PHY_ADDR_OFFSET 8
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#define BIT_WR_DATA_OFFSET 16
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struct hisi_femac_mdio_data {
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struct clk *clk;
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void __iomem *membase;
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};
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static int hisi_femac_mdio_wait_ready(struct hisi_femac_mdio_data *data)
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{
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u32 val;
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return readl_poll_timeout(data->membase + MDIO_RWCTRL,
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val, val & MDIO_RW_FINISH, 20, 10000);
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}
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static int hisi_femac_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
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{
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struct hisi_femac_mdio_data *data = bus->priv;
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int ret;
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ret = hisi_femac_mdio_wait_ready(data);
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if (ret)
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return ret;
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writel((mii_id << BIT_PHY_ADDR_OFFSET) | regnum,
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data->membase + MDIO_RWCTRL);
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ret = hisi_femac_mdio_wait_ready(data);
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if (ret)
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return ret;
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return readl(data->membase + MDIO_RO_DATA) & 0xFFFF;
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}
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static int hisi_femac_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
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u16 value)
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{
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struct hisi_femac_mdio_data *data = bus->priv;
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int ret;
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ret = hisi_femac_mdio_wait_ready(data);
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if (ret)
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return ret;
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writel(MDIO_WRITE | (value << BIT_WR_DATA_OFFSET) |
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(mii_id << BIT_PHY_ADDR_OFFSET) | regnum,
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data->membase + MDIO_RWCTRL);
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return hisi_femac_mdio_wait_ready(data);
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}
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static int hisi_femac_mdio_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct mii_bus *bus;
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struct hisi_femac_mdio_data *data;
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struct resource *res;
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int ret;
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bus = mdiobus_alloc_size(sizeof(*data));
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if (!bus)
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return -ENOMEM;
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bus->name = "hisi_femac_mii_bus";
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bus->read = &hisi_femac_mdio_read;
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bus->write = &hisi_femac_mdio_write;
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snprintf(bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
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bus->parent = &pdev->dev;
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data = bus->priv;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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data->membase = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(data->membase)) {
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ret = PTR_ERR(data->membase);
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goto err_out_free_mdiobus;
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}
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data->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(data->clk)) {
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ret = PTR_ERR(data->clk);
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goto err_out_free_mdiobus;
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}
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ret = clk_prepare_enable(data->clk);
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if (ret)
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goto err_out_free_mdiobus;
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ret = of_mdiobus_register(bus, np);
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if (ret)
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goto err_out_disable_clk;
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platform_set_drvdata(pdev, bus);
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return 0;
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err_out_disable_clk:
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clk_disable_unprepare(data->clk);
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err_out_free_mdiobus:
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mdiobus_free(bus);
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return ret;
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}
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static int hisi_femac_mdio_remove(struct platform_device *pdev)
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{
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struct mii_bus *bus = platform_get_drvdata(pdev);
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struct hisi_femac_mdio_data *data = bus->priv;
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mdiobus_unregister(bus);
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clk_disable_unprepare(data->clk);
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mdiobus_free(bus);
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return 0;
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}
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static const struct of_device_id hisi_femac_mdio_dt_ids[] = {
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{ .compatible = "hisilicon,hisi-femac-mdio" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, hisi_femac_mdio_dt_ids);
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static struct platform_driver hisi_femac_mdio_driver = {
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.probe = hisi_femac_mdio_probe,
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.remove = hisi_femac_mdio_remove,
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.driver = {
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.name = "hisi-femac-mdio",
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.of_match_table = hisi_femac_mdio_dt_ids,
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},
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};
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module_platform_driver(hisi_femac_mdio_driver);
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MODULE_DESCRIPTION("Hisilicon Fast Ethernet MAC MDIO interface driver");
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MODULE_AUTHOR("Dongpo Li <lidongpo@hisilicon.com>");
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MODULE_LICENSE("GPL v2");
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