drm/nv04/gr: move to exec engine interfaces
Like nv10-nv50, needs cleanup. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
d11db27901
commit
4976986bd4
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@ -1141,15 +1141,9 @@ extern int nvc0_fifo_load_context(struct nouveau_channel *);
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extern int nvc0_fifo_unload_context(struct drm_device *);
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/* nv04_graph.c */
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extern int nv04_graph_init(struct drm_device *);
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extern void nv04_graph_takedown(struct drm_device *);
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extern int nv04_graph_create(struct drm_device *);
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extern void nv04_graph_fifo_access(struct drm_device *, bool);
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extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
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extern int nv04_graph_create_context(struct nouveau_channel *);
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extern void nv04_graph_destroy_context(struct nouveau_channel *);
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extern int nv04_graph_load_context(struct nouveau_channel *);
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extern int nv04_graph_unload_context(struct drm_device *);
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extern int nv04_graph_object_new(struct nouveau_channel *, u32, u16);
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extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16);
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extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
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u32 class, u32 mthd, u32 data);
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extern struct nouveau_bitfield nv04_graph_nsource[];
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@ -65,15 +65,10 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->timer.takedown = nv04_timer_takedown;
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engine->fb.init = nv04_fb_init;
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engine->fb.takedown = nv04_fb_takedown;
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engine->graph.init = nv04_graph_init;
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engine->graph.takedown = nv04_graph_takedown;
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engine->graph.fifo_access = nv04_graph_fifo_access;
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engine->graph.channel = nv04_graph_channel;
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engine->graph.create_context = nv04_graph_create_context;
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engine->graph.destroy_context = nv04_graph_destroy_context;
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engine->graph.load_context = nv04_graph_load_context;
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engine->graph.unload_context = nv04_graph_unload_context;
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engine->graph.object_new = nv04_graph_object_new;
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engine->graph.init = nouveau_stub_init;
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engine->graph.takedown = nouveau_stub_takedown;
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engine->graph.channel = nvc0_graph_channel;
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engine->graph.fifo_access = nvc0_graph_fifo_access;
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engine->fifo.channels = 16;
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engine->fifo.init = nv04_fifo_init;
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engine->fifo.takedown = nv04_fifo_fini;
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@ -599,6 +594,9 @@ nouveau_card_init(struct drm_device *dev)
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goto out_timer;
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switch (dev_priv->card_type) {
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case NV_04:
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nv04_graph_create(dev);
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break;
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case NV_10:
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nv10_graph_create(dev);
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break;
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@ -30,8 +30,9 @@
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#include "nouveau_util.h"
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#include "nouveau_ramht.h"
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static int nv04_graph_register(struct drm_device *dev);
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static void nv04_graph_isr(struct drm_device *dev);
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struct nv04_graph_engine {
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struct nouveau_exec_engine base;
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};
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static uint32_t nv04_graph_ctx_regs[] = {
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0x0040053c,
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@ -351,7 +352,7 @@ struct graph_state {
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uint32_t nv04[ARRAY_SIZE(nv04_graph_ctx_regs)];
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};
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struct nouveau_channel *
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static struct nouveau_channel *
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nv04_graph_channel(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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@ -366,26 +367,6 @@ nv04_graph_channel(struct drm_device *dev)
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return dev_priv->channels.ptr[chid];
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}
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static void
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nv04_graph_context_switch(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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struct nouveau_channel *chan = NULL;
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int chid;
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nouveau_wait_for_idle(dev);
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/* If previous context is valid, we need to save it */
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pgraph->unload_context(dev);
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/* Load context for next channel */
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chid = dev_priv->engine.fifo.channel_id(dev);
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chan = dev_priv->channels.ptr[chid];
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if (chan)
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nv04_graph_load_context(chan);
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}
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static uint32_t *ctx_reg(struct graph_state *ctx, uint32_t reg)
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{
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int i;
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@ -398,48 +379,11 @@ static uint32_t *ctx_reg(struct graph_state *ctx, uint32_t reg)
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return NULL;
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}
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int nv04_graph_create_context(struct nouveau_channel *chan)
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{
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struct graph_state *pgraph_ctx;
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NV_DEBUG(chan->dev, "nv04_graph_context_create %d\n", chan->id);
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chan->pgraph_ctx = pgraph_ctx = kzalloc(sizeof(*pgraph_ctx),
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GFP_KERNEL);
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if (pgraph_ctx == NULL)
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return -ENOMEM;
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*ctx_reg(pgraph_ctx, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31;
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return 0;
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}
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void nv04_graph_destroy_context(struct nouveau_channel *chan)
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static int
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nv04_graph_load_context(struct nouveau_channel *chan)
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{
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struct graph_state *pgraph_ctx = chan->engctx[NVOBJ_ENGINE_GR];
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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struct graph_state *pgraph_ctx = chan->pgraph_ctx;
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unsigned long flags;
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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pgraph->fifo_access(dev, false);
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/* Unload the context if it's the currently active one */
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if (pgraph->channel(dev) == chan)
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pgraph->unload_context(dev);
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/* Free the context resources */
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kfree(pgraph_ctx);
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chan->pgraph_ctx = NULL;
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pgraph->fifo_access(dev, true);
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spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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}
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int nv04_graph_load_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct graph_state *pgraph_ctx = chan->pgraph_ctx;
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uint32_t tmp;
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int i;
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@ -457,20 +401,19 @@ int nv04_graph_load_context(struct nouveau_channel *chan)
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return 0;
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}
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int
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static int
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nv04_graph_unload_context(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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struct nouveau_channel *chan = NULL;
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struct graph_state *ctx;
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uint32_t tmp;
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int i;
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chan = pgraph->channel(dev);
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chan = nv04_graph_channel(dev);
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if (!chan)
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return 0;
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ctx = chan->pgraph_ctx;
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ctx = chan->engctx[NVOBJ_ENGINE_GR];
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for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++)
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ctx->nv04[i] = nv_rd32(dev, nv04_graph_ctx_regs[i]);
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@ -482,8 +425,48 @@ nv04_graph_unload_context(struct drm_device *dev)
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return 0;
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}
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static int
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nv04_graph_context_new(struct nouveau_channel *chan, int engine)
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{
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struct graph_state *pgraph_ctx;
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NV_DEBUG(chan->dev, "nv04_graph_context_create %d\n", chan->id);
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pgraph_ctx = kzalloc(sizeof(*pgraph_ctx), GFP_KERNEL);
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if (pgraph_ctx == NULL)
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return -ENOMEM;
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*ctx_reg(pgraph_ctx, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31;
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chan->engctx[engine] = pgraph_ctx;
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return 0;
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}
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static void
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nv04_graph_context_del(struct nouveau_channel *chan, int engine)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct graph_state *pgraph_ctx = chan->engctx[engine];
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unsigned long flags;
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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nv04_graph_fifo_access(dev, false);
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/* Unload the context if it's the currently active one */
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if (nv04_graph_channel(dev) == chan)
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nv04_graph_unload_context(dev);
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nv04_graph_fifo_access(dev, true);
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spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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/* Free the context resources */
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kfree(pgraph_ctx);
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chan->engctx[engine] = NULL;
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}
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int
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nv04_graph_object_new(struct nouveau_channel *chan, u32 handle, u16 class)
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nv04_graph_object_new(struct nouveau_channel *chan, int engine,
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u32 handle, u16 class)
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{
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struct drm_device *dev = chan->dev;
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struct nouveau_gpuobj *obj = NULL;
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@ -509,23 +492,18 @@ nv04_graph_object_new(struct nouveau_channel *chan, u32 handle, u16 class)
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return ret;
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}
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int nv04_graph_init(struct drm_device *dev)
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static int
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nv04_graph_init(struct drm_device *dev, int engine)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t tmp;
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int ret;
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nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
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~NV_PMC_ENABLE_PGRAPH);
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nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
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NV_PMC_ENABLE_PGRAPH);
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ret = nv04_graph_register(dev);
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if (ret)
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return ret;
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/* Enable PGRAPH interrupts */
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nouveau_irq_register(dev, 12, nv04_graph_isr);
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nv_wr32(dev, NV03_PGRAPH_INTR, 0xFFFFFFFF);
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nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
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@ -559,10 +537,12 @@ int nv04_graph_init(struct drm_device *dev)
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return 0;
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}
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void nv04_graph_takedown(struct drm_device *dev)
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static int
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nv04_graph_fini(struct drm_device *dev, int engine)
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{
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nv04_graph_unload_context(dev);
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nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000);
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nouveau_irq_unregister(dev, 12);
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return 0;
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}
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void
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@ -997,13 +977,138 @@ nv04_graph_mthd_bind_chroma(struct nouveau_channel *chan,
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return 1;
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}
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static int
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nv04_graph_register(struct drm_device *dev)
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static struct nouveau_bitfield nv04_graph_intr[] = {
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{ NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
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{}
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};
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static struct nouveau_bitfield nv04_graph_nstatus[] = {
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{ NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
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{ NV04_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
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{ NV04_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
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{ NV04_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" },
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{}
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};
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struct nouveau_bitfield nv04_graph_nsource[] = {
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{ NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" },
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{ NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" },
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{ NV03_PGRAPH_NSOURCE_PROTECTION_ERROR, "PROTECTION_ERROR" },
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{ NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION, "RANGE_EXCEPTION" },
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{ NV03_PGRAPH_NSOURCE_LIMIT_COLOR, "LIMIT_COLOR" },
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{ NV03_PGRAPH_NSOURCE_LIMIT_ZETA, "LIMIT_ZETA" },
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{ NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD, "ILLEGAL_MTHD" },
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{ NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION, "DMA_R_PROTECTION" },
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{ NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION, "DMA_W_PROTECTION" },
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{ NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION, "FORMAT_EXCEPTION" },
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{ NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION, "PATCH_EXCEPTION" },
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{ NV03_PGRAPH_NSOURCE_STATE_INVALID, "STATE_INVALID" },
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{ NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY, "DOUBLE_NOTIFY" },
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{ NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE, "NOTIFY_IN_USE" },
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{ NV03_PGRAPH_NSOURCE_METHOD_CNT, "METHOD_CNT" },
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{ NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION, "BFR_NOTIFICATION" },
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{ NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
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{ NV03_PGRAPH_NSOURCE_DMA_WIDTH_A, "DMA_WIDTH_A" },
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{ NV03_PGRAPH_NSOURCE_DMA_WIDTH_B, "DMA_WIDTH_B" },
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{}
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};
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static void
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nv04_graph_context_switch(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_channel *chan = NULL;
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int chid;
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if (dev_priv->engine.graph.registered)
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return 0;
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nouveau_wait_for_idle(dev);
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/* If previous context is valid, we need to save it */
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nv04_graph_unload_context(dev);
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/* Load context for next channel */
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chid = dev_priv->engine.fifo.channel_id(dev);
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chan = dev_priv->channels.ptr[chid];
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if (chan)
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nv04_graph_load_context(chan);
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}
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static void
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nv04_graph_isr(struct drm_device *dev)
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{
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u32 stat;
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while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
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u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
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u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
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u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
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u32 chid = (addr & 0x0f000000) >> 24;
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u32 subc = (addr & 0x0000e000) >> 13;
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u32 mthd = (addr & 0x00001ffc);
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u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
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u32 class = nv_rd32(dev, 0x400180 + subc * 4) & 0xff;
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u32 show = stat;
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if (stat & NV_PGRAPH_INTR_NOTIFY) {
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if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
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if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
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show &= ~NV_PGRAPH_INTR_NOTIFY;
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}
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}
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if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
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nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
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stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
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show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
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nv04_graph_context_switch(dev);
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}
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nv_wr32(dev, NV03_PGRAPH_INTR, stat);
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nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
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if (show && nouveau_ratelimit()) {
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NV_INFO(dev, "PGRAPH -");
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nouveau_bitfield_print(nv04_graph_intr, show);
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printk(" nsource:");
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nouveau_bitfield_print(nv04_graph_nsource, nsource);
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printk(" nstatus:");
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nouveau_bitfield_print(nv04_graph_nstatus, nstatus);
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printk("\n");
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NV_INFO(dev, "PGRAPH - ch %d/%d class 0x%04x "
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"mthd 0x%04x data 0x%08x\n",
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chid, subc, class, mthd, data);
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}
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}
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}
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static void
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nv04_graph_destroy(struct drm_device *dev, int engine)
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{
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struct nv04_graph_engine *pgraph = nv_engine(dev, engine);
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nouveau_irq_unregister(dev, 12);
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NVOBJ_ENGINE_DEL(dev, GR);
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kfree(pgraph);
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}
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int
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nv04_graph_create(struct drm_device *dev)
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{
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struct nv04_graph_engine *pgraph;
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pgraph = kzalloc(sizeof(*pgraph), GFP_KERNEL);
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if (!pgraph)
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return -ENOMEM;
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pgraph->base.destroy = nv04_graph_destroy;
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pgraph->base.init = nv04_graph_init;
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pgraph->base.fini = nv04_graph_fini;
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pgraph->base.context_new = nv04_graph_context_new;
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pgraph->base.context_del = nv04_graph_context_del;
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pgraph->base.object_new = nv04_graph_object_new;
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NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
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nouveau_irq_register(dev, 12, nv04_graph_isr);
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/* dvd subpicture */
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NVOBJ_CLASS(dev, 0x0038, GR);
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@ -1250,91 +1355,5 @@ nv04_graph_register(struct drm_device *dev)
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NVOBJ_CLASS(dev, 0x506e, SW);
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NVOBJ_MTHD (dev, 0x506e, 0x0150, nv04_graph_mthd_set_ref);
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NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
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dev_priv->engine.graph.registered = true;
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return 0;
|
||||
};
|
||||
|
||||
static struct nouveau_bitfield nv04_graph_intr[] = {
|
||||
{ NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct nouveau_bitfield nv04_graph_nstatus[] = {
|
||||
{ NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
|
||||
{ NV04_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
|
||||
{ NV04_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
|
||||
{ NV04_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" },
|
||||
{}
|
||||
};
|
||||
|
||||
struct nouveau_bitfield nv04_graph_nsource[] = {
|
||||
{ NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" },
|
||||
{ NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" },
|
||||
{ NV03_PGRAPH_NSOURCE_PROTECTION_ERROR, "PROTECTION_ERROR" },
|
||||
{ NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION, "RANGE_EXCEPTION" },
|
||||
{ NV03_PGRAPH_NSOURCE_LIMIT_COLOR, "LIMIT_COLOR" },
|
||||
{ NV03_PGRAPH_NSOURCE_LIMIT_ZETA, "LIMIT_ZETA" },
|
||||
{ NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD, "ILLEGAL_MTHD" },
|
||||
{ NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION, "DMA_R_PROTECTION" },
|
||||
{ NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION, "DMA_W_PROTECTION" },
|
||||
{ NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION, "FORMAT_EXCEPTION" },
|
||||
{ NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION, "PATCH_EXCEPTION" },
|
||||
{ NV03_PGRAPH_NSOURCE_STATE_INVALID, "STATE_INVALID" },
|
||||
{ NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY, "DOUBLE_NOTIFY" },
|
||||
{ NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE, "NOTIFY_IN_USE" },
|
||||
{ NV03_PGRAPH_NSOURCE_METHOD_CNT, "METHOD_CNT" },
|
||||
{ NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION, "BFR_NOTIFICATION" },
|
||||
{ NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
|
||||
{ NV03_PGRAPH_NSOURCE_DMA_WIDTH_A, "DMA_WIDTH_A" },
|
||||
{ NV03_PGRAPH_NSOURCE_DMA_WIDTH_B, "DMA_WIDTH_B" },
|
||||
{}
|
||||
};
|
||||
|
||||
static void
|
||||
nv04_graph_isr(struct drm_device *dev)
|
||||
{
|
||||
u32 stat;
|
||||
|
||||
while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
|
||||
u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
|
||||
u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
|
||||
u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
|
||||
u32 chid = (addr & 0x0f000000) >> 24;
|
||||
u32 subc = (addr & 0x0000e000) >> 13;
|
||||
u32 mthd = (addr & 0x00001ffc);
|
||||
u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
|
||||
u32 class = nv_rd32(dev, 0x400180 + subc * 4) & 0xff;
|
||||
u32 show = stat;
|
||||
|
||||
if (stat & NV_PGRAPH_INTR_NOTIFY) {
|
||||
if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
|
||||
if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
|
||||
show &= ~NV_PGRAPH_INTR_NOTIFY;
|
||||
}
|
||||
}
|
||||
|
||||
if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
|
||||
nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
|
||||
stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
|
||||
show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
|
||||
nv04_graph_context_switch(dev);
|
||||
}
|
||||
|
||||
nv_wr32(dev, NV03_PGRAPH_INTR, stat);
|
||||
nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
|
||||
|
||||
if (show && nouveau_ratelimit()) {
|
||||
NV_INFO(dev, "PGRAPH -");
|
||||
nouveau_bitfield_print(nv04_graph_intr, show);
|
||||
printk(" nsource:");
|
||||
nouveau_bitfield_print(nv04_graph_nsource, nsource);
|
||||
printk(" nstatus:");
|
||||
nouveau_bitfield_print(nv04_graph_nstatus, nstatus);
|
||||
printk("\n");
|
||||
NV_INFO(dev, "PGRAPH - ch %d/%d class 0x%04x "
|
||||
"mthd 0x%04x data 0x%08x\n",
|
||||
chid, subc, class, mthd, data);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
Loading…
Reference in a new issue