[PATCH] ppc32: add bamboo platform
Add Bamboo platform support. This is an AMCC 440EP-based reference platform. Signed-off-by: Wade Farnsworth <wfarnsworth@mvista.com> Signed-off-by: Matt Porter <mporter@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Matt Porter
Linus Torvalds
parent
c9cf73aee1
commit
497799d368
427
arch/ppc/platforms/4xx/bamboo.c
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427
arch/ppc/platforms/4xx/bamboo.c
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/*
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* arch/ppc/platforms/4xx/bamboo.c
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*
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* Bamboo board specific routines
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*
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* Wade Farnsworth <wfarnsworth@mvista.com>
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* Copyright 2004 MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/types.h>
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#include <linux/major.h>
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#include <linux/blkdev.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/ide.h>
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#include <linux/initrd.h>
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#include <linux/irq.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <linux/tty.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/ethtool.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/dma.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/ocp.h>
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#include <asm/pci-bridge.h>
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#include <asm/time.h>
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#include <asm/todc.h>
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#include <asm/bootinfo.h>
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#include <asm/ppc4xx_pic.h>
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#include <asm/ppcboot.h>
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#include <syslib/gen550.h>
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#include <syslib/ibm440gx_common.h>
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/*
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* This is a horrible kludge, we eventually need to abstract this
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* generic PHY stuff, so the standard phy mode defines can be
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* easily used from arch code.
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*/
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#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
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bd_t __res;
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static struct ibm44x_clocks clocks __initdata;
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/*
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* Bamboo external IRQ triggering/polarity settings
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*/
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unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: Ethernet transceiver */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ1: Expansion connector */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 0 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 1 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ4: PCI slot 2 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ5: PCI slot 3 */
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(IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ6: SMI pushbutton */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ7: EXT */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
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};
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static void __init
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bamboo_calibrate_decr(void)
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{
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unsigned int freq;
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if (mfspr(SPRN_CCR1) & CCR1_TCS)
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freq = BAMBOO_TMRCLK;
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else
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freq = clocks.cpu;
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ibm44x_calibrate_decr(freq);
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}
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static int
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bamboo_show_cpuinfo(struct seq_file *m)
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{
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seq_printf(m, "vendor\t\t: IBM\n");
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seq_printf(m, "machine\t\t: PPC440EP EVB (Bamboo)\n");
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return 0;
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}
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static inline int
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bamboo_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{ 28, 28, 28, 28 }, /* IDSEL 1 - PCI Slot 0 */
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{ 27, 27, 27, 27 }, /* IDSEL 2 - PCI Slot 1 */
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{ 26, 26, 26, 26 }, /* IDSEL 3 - PCI Slot 2 */
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{ 25, 25, 25, 25 }, /* IDSEL 4 - PCI Slot 3 */
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};
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const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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}
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static void __init bamboo_set_emacdata(void)
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{
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unsigned char * selection1_base;
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struct ocp_def *def;
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struct ocp_func_emac_data *emacdata;
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u8 selection1_val;
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int mode;
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selection1_base = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16);
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selection1_val = readb(selection1_base);
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iounmap((void *) selection1_base);
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if (BAMBOO_SEL_MII(selection1_val))
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mode = PHY_MODE_MII;
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else if (BAMBOO_SEL_RMII(selection1_val))
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mode = PHY_MODE_RMII;
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else
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mode = PHY_MODE_SMII;
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/* Set mac_addr and phy mode for each EMAC */
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def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
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emacdata = def->additions;
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memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
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emacdata->phy_mode = mode;
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def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
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emacdata = def->additions;
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memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
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emacdata->phy_mode = mode;
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}
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static int
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bamboo_exclude_device(unsigned char bus, unsigned char devfn)
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{
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return (bus == 0 && devfn == 0);
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}
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#define PCI_READW(offset) \
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(readw((void *)((u32)pci_reg_base+offset)))
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#define PCI_WRITEW(value, offset) \
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(writew(value, (void *)((u32)pci_reg_base+offset)))
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#define PCI_WRITEL(value, offset) \
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(writel(value, (void *)((u32)pci_reg_base+offset)))
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static void __init
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bamboo_setup_pci(void)
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{
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void *pci_reg_base;
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unsigned long memory_size;
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memory_size = ppc_md.find_end_of_memory();
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pci_reg_base = ioremap64(BAMBOO_PCIL0_BASE, BAMBOO_PCIL0_SIZE);
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/* Enable PCI I/O, Mem, and Busmaster cycles */
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PCI_WRITEW(PCI_READW(PCI_COMMAND) |
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER, PCI_COMMAND);
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/* Disable region first */
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PCI_WRITEL(0, BAMBOO_PCIL0_PMM0MA);
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/* PLB starting addr: 0x00000000A0000000 */
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PCI_WRITEL(BAMBOO_PCI_PHY_MEM_BASE, BAMBOO_PCIL0_PMM0LA);
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/* PCI start addr, 0xA0000000 (PCI Address) */
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PCI_WRITEL(BAMBOO_PCI_MEM_BASE, BAMBOO_PCIL0_PMM0PCILA);
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PCI_WRITEL(0, BAMBOO_PCIL0_PMM0PCIHA);
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/* Enable no pre-fetch, enable region */
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PCI_WRITEL(((0xffffffff -
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(BAMBOO_PCI_UPPER_MEM - BAMBOO_PCI_MEM_BASE)) | 0x01),
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BAMBOO_PCIL0_PMM0MA);
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/* Disable region one */
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PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
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PCI_WRITEL(0, BAMBOO_PCIL0_PMM1LA);
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PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCILA);
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PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCIHA);
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PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
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/* Disable region two */
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PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
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PCI_WRITEL(0, BAMBOO_PCIL0_PMM2LA);
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PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCILA);
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PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCIHA);
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PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
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/* Now configure the PCI->PLB windows, we only use PTM1
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*
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* For Inbound flow, set the window size to all available memory
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* This is required because if size is smaller,
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* then Eth/PCI DD would fail as PCI card not able to access
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* the memory allocated by DD.
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*/
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PCI_WRITEL(0, BAMBOO_PCIL0_PTM1MS); /* disabled region 1 */
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PCI_WRITEL(0, BAMBOO_PCIL0_PTM1LA); /* begin of address map */
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memory_size = 1 << fls(memory_size - 1);
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/* Size low + Enabled */
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PCI_WRITEL((0xffffffff - (memory_size - 1)) | 0x1, BAMBOO_PCIL0_PTM1MS);
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eieio();
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iounmap(pci_reg_base);
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}
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static void __init
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bamboo_setup_hose(void)
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{
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unsigned int bar_response, bar;
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struct pci_controller *hose;
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bamboo_setup_pci();
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hose = pcibios_alloc_controller();
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if (!hose)
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return;
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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hose->pci_mem_offset = BAMBOO_PCI_MEM_OFFSET;
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pci_init_resource(&hose->io_resource,
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BAMBOO_PCI_LOWER_IO,
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BAMBOO_PCI_UPPER_IO,
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IORESOURCE_IO,
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"PCI host bridge");
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pci_init_resource(&hose->mem_resources[0],
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BAMBOO_PCI_LOWER_MEM,
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BAMBOO_PCI_UPPER_MEM,
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IORESOURCE_MEM,
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"PCI host bridge");
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ppc_md.pci_exclude_device = bamboo_exclude_device;
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hose->io_space.start = BAMBOO_PCI_LOWER_IO;
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hose->io_space.end = BAMBOO_PCI_UPPER_IO;
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hose->mem_space.start = BAMBOO_PCI_LOWER_MEM;
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hose->mem_space.end = BAMBOO_PCI_UPPER_MEM;
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isa_io_base =
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(unsigned long)ioremap64(BAMBOO_PCI_IO_BASE, BAMBOO_PCI_IO_SIZE);
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hose->io_base_virt = (void *)isa_io_base;
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setup_indirect_pci(hose,
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BAMBOO_PCI_CFGA_PLB32,
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BAMBOO_PCI_CFGD_PLB32);
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hose->set_cfg_type = 1;
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/* Zero config bars */
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for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
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early_write_config_dword(hose, hose->first_busno,
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PCI_FUNC(hose->first_busno), bar,
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0x00000000);
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early_read_config_dword(hose, hose->first_busno,
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PCI_FUNC(hose->first_busno), bar,
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&bar_response);
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}
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hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
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ppc_md.pci_swizzle = common_swizzle;
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ppc_md.pci_map_irq = bamboo_map_irq;
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}
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TODC_ALLOC();
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static void __init
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bamboo_early_serial_map(void)
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{
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struct uart_port port;
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/* Setup ioremapped serial port access */
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memset(&port, 0, sizeof(port));
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port.membase = ioremap64(PPC440EP_UART0_ADDR, 8);
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port.irq = 0;
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port.uartclk = clocks.uart0;
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port.regshift = 0;
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port.iotype = SERIAL_IO_MEM;
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port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
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port.line = 0;
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if (early_serial_setup(&port) != 0) {
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printk("Early serial init of port 0 failed\n");
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}
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#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
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/* Configure debug serial access */
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gen550_init(0, &port);
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#endif
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port.membase = ioremap64(PPC440EP_UART1_ADDR, 8);
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port.irq = 1;
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port.uartclk = clocks.uart1;
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port.line = 1;
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if (early_serial_setup(&port) != 0) {
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printk("Early serial init of port 1 failed\n");
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}
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#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
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/* Configure debug serial access */
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gen550_init(1, &port);
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#endif
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port.membase = ioremap64(PPC440EP_UART2_ADDR, 8);
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port.irq = 3;
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port.uartclk = clocks.uart2;
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port.line = 2;
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if (early_serial_setup(&port) != 0) {
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printk("Early serial init of port 2 failed\n");
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}
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#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
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/* Configure debug serial access */
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gen550_init(2, &port);
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#endif
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port.membase = ioremap64(PPC440EP_UART3_ADDR, 8);
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port.irq = 4;
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port.uartclk = clocks.uart3;
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port.line = 3;
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if (early_serial_setup(&port) != 0) {
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printk("Early serial init of port 3 failed\n");
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}
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}
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static void __init
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bamboo_setup_arch(void)
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{
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bamboo_set_emacdata();
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ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
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ocp_sys_info.opb_bus_freq = clocks.opb;
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/* Setup TODC access */
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TODC_INIT(TODC_TYPE_DS1743,
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0,
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0,
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ioremap64(BAMBOO_RTC_ADDR, BAMBOO_RTC_SIZE),
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8);
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/* init to some ~sane value until calibrate_delay() runs */
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loops_per_jiffy = 50000000/HZ;
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/* Setup PCI host bridge */
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bamboo_setup_hose();
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#ifdef CONFIG_BLK_DEV_INITRD
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if (initrd_start)
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ROOT_DEV = Root_RAM0;
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else
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#endif
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#ifdef CONFIG_ROOT_NFS
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ROOT_DEV = Root_NFS;
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#else
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ROOT_DEV = Root_HDA1;
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#endif
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bamboo_early_serial_map();
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/* Identify the system */
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printk("IBM Bamboo port (MontaVista Software, Inc. (source@mvista.com))\n");
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}
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void __init platform_init(unsigned long r3, unsigned long r4,
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unsigned long r5, unsigned long r6, unsigned long r7)
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{
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parse_bootinfo(find_bootinfo());
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/*
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* If we were passed in a board information, copy it into the
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* residual data area.
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*/
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if (r3)
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__res = *(bd_t *)(r3 + KERNELBASE);
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ibm44x_platform_init();
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ppc_md.setup_arch = bamboo_setup_arch;
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ppc_md.show_cpuinfo = bamboo_show_cpuinfo;
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ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
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ppc_md.calibrate_decr = bamboo_calibrate_decr;
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ppc_md.time_init = todc_time_init;
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ppc_md.set_rtc_time = todc_set_rtc_time;
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ppc_md.get_rtc_time = todc_get_rtc_time;
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ppc_md.nvram_read_val = todc_direct_read_val;
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ppc_md.nvram_write_val = todc_direct_write_val;
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#ifdef CONFIG_KGDB
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ppc_md.early_serial_map = bamboo_early_serial_map;
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#endif
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}
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136
arch/ppc/platforms/4xx/bamboo.h
Normal file
136
arch/ppc/platforms/4xx/bamboo.h
Normal file
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@ -0,0 +1,136 @@
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/*
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* arch/ppc/platforms/bamboo.h
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*
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* Bamboo board definitions
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*
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* Wade Farnsworth <wfarnsworth@mvista.com>
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*
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* Copyright 2004 MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#ifdef __KERNEL__
|
||||
#ifndef __ASM_BAMBOO_H__
|
||||
#define __ASM_BAMBOO_H__
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <platforms/4xx/ibm440ep.h>
|
||||
|
||||
/* F/W TLB mapping used in bootloader glue to reset EMAC */
|
||||
#define PPC44x_EMAC0_MR0 0x0EF600E00
|
||||
|
||||
/* Location of MAC addresses in PIBS image */
|
||||
#define PIBS_FLASH_BASE 0xfff00000
|
||||
#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0xc0400)
|
||||
#define PIBS_MAC_SIZE 0x200
|
||||
#define PIBS_MAC_OFFSET 0x100
|
||||
|
||||
/* Default clock rate */
|
||||
#define BAMBOO_TMRCLK 25000000
|
||||
|
||||
/* RTC/NVRAM location */
|
||||
#define BAMBOO_RTC_ADDR 0x080000000ULL
|
||||
#define BAMBOO_RTC_SIZE 0x2000
|
||||
|
||||
/* FPGA Registers */
|
||||
#define BAMBOO_FPGA_ADDR 0x080002000ULL
|
||||
|
||||
#define BAMBOO_FPGA_CONFIG2_REG_ADDR (BAMBOO_FPGA_ADDR + 0x1)
|
||||
#define BAMBOO_FULL_DUPLEX_EN(x) (x & 0x08)
|
||||
#define BAMBOO_FORCE_100Mbps(x) (x & 0x04)
|
||||
#define BAMBOO_AUTONEGOTIATE(x) (x & 0x02)
|
||||
|
||||
#define BAMBOO_FPGA_SETTING_REG_ADDR (BAMBOO_FPGA_ADDR + 0x3)
|
||||
#define BAMBOO_BOOT_SMALL_FLASH(x) (!(x & 0x80))
|
||||
#define BAMBOO_LARGE_FLASH_EN(x) (!(x & 0x40))
|
||||
#define BAMBOO_BOOT_NAND_FLASH(x) (!(x & 0x20))
|
||||
|
||||
#define BAMBOO_FPGA_SELECTION1_REG_ADDR (BAMBOO_FPGA_ADDR + 0x4)
|
||||
#define BAMBOO_SEL_MII(x) (x & 0x80)
|
||||
#define BAMBOO_SEL_RMII(x) (x & 0x40)
|
||||
#define BAMBOO_SEL_SMII(x) (x & 0x20)
|
||||
|
||||
/* Flash */
|
||||
#define BAMBOO_SMALL_FLASH_LOW 0x087f00000ULL
|
||||
#define BAMBOO_SMALL_FLASH_HIGH 0x0fff00000ULL
|
||||
#define BAMBOO_SMALL_FLASH_SIZE 0x100000
|
||||
#define BAMBOO_LARGE_FLASH_LOW 0x087800000ULL
|
||||
#define BAMBOO_LARGE_FLASH_HIGH1 0x0ff800000ULL
|
||||
#define BAMBOO_LARGE_FLASH_HIGH2 0x0ffc00000ULL
|
||||
#define BAMBOO_LARGE_FLASH_SIZE 0x400000
|
||||
#define BAMBOO_SRAM_LOW 0x087f00000ULL
|
||||
#define BAMBOO_SRAM_HIGH1 0x0fff00000ULL
|
||||
#define BAMBOO_SRAM_HIGH2 0x0ff800000ULL
|
||||
#define BAMBOO_SRAM_SIZE 0x100000
|
||||
#define BAMBOO_NAND_FLASH_REG_ADDR 0x090000000ULL
|
||||
#define BAMBOO_NAND_FLASH_REG_SIZE 0x2000
|
||||
|
||||
/*
|
||||
* Serial port defines
|
||||
*/
|
||||
#define RS_TABLE_SIZE 4
|
||||
|
||||
#define UART0_IO_BASE 0xEF600300
|
||||
#define UART1_IO_BASE 0xEF600400
|
||||
#define UART2_IO_BASE 0xEF600500
|
||||
#define UART3_IO_BASE 0xEF600600
|
||||
|
||||
#define BASE_BAUD 33177600/3/16
|
||||
#define UART0_INT 0
|
||||
#define UART1_INT 1
|
||||
#define UART2_INT 3
|
||||
#define UART3_INT 4
|
||||
|
||||
#define STD_UART_OP(num) \
|
||||
{ 0, BASE_BAUD, 0, UART##num##_INT, \
|
||||
(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
|
||||
iomem_base: UART##num##_IO_BASE, \
|
||||
io_type: SERIAL_IO_MEM},
|
||||
|
||||
#define SERIAL_PORT_DFNS \
|
||||
STD_UART_OP(0) \
|
||||
STD_UART_OP(1) \
|
||||
STD_UART_OP(2) \
|
||||
STD_UART_OP(3)
|
||||
|
||||
/* PCI support */
|
||||
#define BAMBOO_PCI_CFGA_PLB32 0xeec00000
|
||||
#define BAMBOO_PCI_CFGD_PLB32 0xeec00004
|
||||
|
||||
#define BAMBOO_PCI_IO_BASE 0x00000000e8000000ULL
|
||||
#define BAMBOO_PCI_IO_SIZE 0x00010000
|
||||
#define BAMBOO_PCI_MEM_OFFSET 0x00000000
|
||||
#define BAMBOO_PCI_PHY_MEM_BASE 0x00000000a0000000ULL
|
||||
|
||||
#define BAMBOO_PCI_LOWER_IO 0x00000000
|
||||
#define BAMBOO_PCI_UPPER_IO 0x0000ffff
|
||||
#define BAMBOO_PCI_LOWER_MEM 0xa0000000
|
||||
#define BAMBOO_PCI_UPPER_MEM 0xafffffff
|
||||
#define BAMBOO_PCI_MEM_BASE 0xa0000000
|
||||
|
||||
#define BAMBOO_PCIL0_BASE 0x00000000ef400000ULL
|
||||
#define BAMBOO_PCIL0_SIZE 0x40
|
||||
|
||||
#define BAMBOO_PCIL0_PMM0LA 0x000
|
||||
#define BAMBOO_PCIL0_PMM0MA 0x004
|
||||
#define BAMBOO_PCIL0_PMM0PCILA 0x008
|
||||
#define BAMBOO_PCIL0_PMM0PCIHA 0x00C
|
||||
#define BAMBOO_PCIL0_PMM1LA 0x010
|
||||
#define BAMBOO_PCIL0_PMM1MA 0x014
|
||||
#define BAMBOO_PCIL0_PMM1PCILA 0x018
|
||||
#define BAMBOO_PCIL0_PMM1PCIHA 0x01C
|
||||
#define BAMBOO_PCIL0_PMM2LA 0x020
|
||||
#define BAMBOO_PCIL0_PMM2MA 0x024
|
||||
#define BAMBOO_PCIL0_PMM2PCILA 0x028
|
||||
#define BAMBOO_PCIL0_PMM2PCIHA 0x02C
|
||||
#define BAMBOO_PCIL0_PTM1MS 0x030
|
||||
#define BAMBOO_PCIL0_PTM1LA 0x034
|
||||
#define BAMBOO_PCIL0_PTM2MS 0x038
|
||||
#define BAMBOO_PCIL0_PTM2LA 0x03C
|
||||
|
||||
#endif /* __ASM_BAMBOO_H__ */
|
||||
#endif /* __KERNEL__ */
|
||||
Loading…
Reference in a new issue