[SCSI] 3ware 9000: Add support for 9550SX controllers
Signed-off-by: Adam Radford <linuxraid@amcc.com> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>hifive-unleashed-5.1
adam radford
James Bottomley
parent
68ce1eb540
commit
49bfd8db4a
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@ -60,6 +60,7 @@
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Remove un-needed eh_abort handler.
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Add support for embedded firmware error strings.
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2.26.02.003 - Correctly handle single sgl's with use_sg=1.
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2.26.02.004 - Add support for 9550SX controllers.
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*/
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#include <linux/module.h>
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@ -82,7 +83,7 @@
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#include "3w-9xxx.h"
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/* Globals */
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#define TW_DRIVER_VERSION "2.26.02.003"
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#define TW_DRIVER_VERSION "2.26.02.004"
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static TW_Device_Extension *twa_device_extension_list[TW_MAX_SLOT];
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static unsigned int twa_device_extension_count;
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static int twa_major = -1;
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@ -892,11 +893,6 @@ static int twa_decode_bits(TW_Device_Extension *tw_dev, u32 status_reg_value)
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writel(TW_CONTROL_CLEAR_QUEUE_ERROR, TW_CONTROL_REG_ADDR(tw_dev));
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}
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if (status_reg_value & TW_STATUS_SBUF_WRITE_ERROR) {
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TW_PRINTK(tw_dev->host, TW_DRIVER, 0xf, "SBUF Write Error: clearing");
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writel(TW_CONTROL_CLEAR_SBUF_WRITE_ERROR, TW_CONTROL_REG_ADDR(tw_dev));
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}
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if (status_reg_value & TW_STATUS_MICROCONTROLLER_ERROR) {
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if (tw_dev->reset_print == 0) {
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TW_PRINTK(tw_dev->host, TW_DRIVER, 0x10, "Microcontroller Error: clearing");
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@ -930,6 +926,36 @@ out:
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return retval;
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} /* End twa_empty_response_queue() */
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/* This function will clear the pchip/response queue on 9550SX */
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static int twa_empty_response_queue_large(TW_Device_Extension *tw_dev)
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{
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u32 status_reg_value, response_que_value;
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int count = 0, retval = 1;
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if (tw_dev->tw_pci_dev->device == PCI_DEVICE_ID_3WARE_9550SX) {
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status_reg_value = readl(TW_STATUS_REG_ADDR(tw_dev));
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while (((status_reg_value & TW_STATUS_RESPONSE_QUEUE_EMPTY) == 0) && (count < TW_MAX_RESPONSE_DRAIN)) {
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response_que_value = readl(TW_RESPONSE_QUEUE_REG_ADDR_LARGE(tw_dev));
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if ((response_que_value & TW_9550SX_DRAIN_COMPLETED) == TW_9550SX_DRAIN_COMPLETED) {
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/* P-chip settle time */
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msleep(500);
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retval = 0;
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goto out;
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}
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status_reg_value = readl(TW_STATUS_REG_ADDR(tw_dev));
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count++;
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}
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if (count == TW_MAX_RESPONSE_DRAIN)
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goto out;
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retval = 0;
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} else
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retval = 0;
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out:
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return retval;
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} /* End twa_empty_response_queue_large() */
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/* This function passes sense keys from firmware to scsi layer */
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static int twa_fill_sense(TW_Device_Extension *tw_dev, int request_id, int copy_sense, int print_host)
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{
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@ -1613,8 +1639,16 @@ static int twa_reset_sequence(TW_Device_Extension *tw_dev, int soft_reset)
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int tries = 0, retval = 1, flashed = 0, do_soft_reset = soft_reset;
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while (tries < TW_MAX_RESET_TRIES) {
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if (do_soft_reset)
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if (do_soft_reset) {
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TW_SOFT_RESET(tw_dev);
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/* Clear pchip/response queue on 9550SX */
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if (twa_empty_response_queue_large(tw_dev)) {
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TW_PRINTK(tw_dev->host, TW_DRIVER, 0x36, "Response queue (large) empty failed during reset sequence");
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do_soft_reset = 1;
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tries++;
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continue;
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}
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}
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/* Make sure controller is in a good state */
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if (twa_poll_status(tw_dev, TW_STATUS_MICROCONTROLLER_READY | (do_soft_reset == 1 ? TW_STATUS_ATTENTION_INTERRUPT : 0), 60)) {
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@ -2034,7 +2068,10 @@ static int __devinit twa_probe(struct pci_dev *pdev, const struct pci_device_id
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goto out_free_device_extension;
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}
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mem_addr = pci_resource_start(pdev, 1);
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if (pdev->device == PCI_DEVICE_ID_3WARE_9000)
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mem_addr = pci_resource_start(pdev, 1);
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else
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mem_addr = pci_resource_start(pdev, 2);
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/* Save base address */
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tw_dev->base_addr = ioremap(mem_addr, PAGE_SIZE);
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@ -2148,6 +2185,8 @@ static void twa_remove(struct pci_dev *pdev)
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static struct pci_device_id twa_pci_tbl[] __devinitdata = {
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{ PCI_VENDOR_ID_3WARE, PCI_DEVICE_ID_3WARE_9000,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
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{ PCI_VENDOR_ID_3WARE, PCI_DEVICE_ID_3WARE_9550SX,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
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{ }
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};
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MODULE_DEVICE_TABLE(pci, twa_pci_tbl);
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@ -267,7 +267,6 @@ static twa_message_type twa_error_table[] = {
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#define TW_CONTROL_CLEAR_PARITY_ERROR 0x00800000
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#define TW_CONTROL_CLEAR_QUEUE_ERROR 0x00400000
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#define TW_CONTROL_CLEAR_PCI_ABORT 0x00100000
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#define TW_CONTROL_CLEAR_SBUF_WRITE_ERROR 0x00000008
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/* Status register bit definitions */
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#define TW_STATUS_MAJOR_VERSION_MASK 0xF0000000
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@ -285,9 +284,8 @@ static twa_message_type twa_error_table[] = {
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#define TW_STATUS_MICROCONTROLLER_READY 0x00002000
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#define TW_STATUS_COMMAND_QUEUE_EMPTY 0x00001000
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#define TW_STATUS_EXPECTED_BITS 0x00002000
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#define TW_STATUS_UNEXPECTED_BITS 0x00F00008
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#define TW_STATUS_SBUF_WRITE_ERROR 0x00000008
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#define TW_STATUS_VALID_INTERRUPT 0x00DF0008
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#define TW_STATUS_UNEXPECTED_BITS 0x00F00000
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#define TW_STATUS_VALID_INTERRUPT 0x00DF0000
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/* RESPONSE QUEUE BIT DEFINITIONS */
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#define TW_RESPONSE_ID_MASK 0x00000FF0
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@ -324,9 +322,9 @@ static twa_message_type twa_error_table[] = {
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/* Compatibility defines */
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#define TW_9000_ARCH_ID 0x5
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#define TW_CURRENT_DRIVER_SRL 28
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#define TW_CURRENT_DRIVER_BUILD 9
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#define TW_CURRENT_DRIVER_BRANCH 4
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#define TW_CURRENT_DRIVER_SRL 30
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#define TW_CURRENT_DRIVER_BUILD 80
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#define TW_CURRENT_DRIVER_BRANCH 0
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/* Phase defines */
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#define TW_PHASE_INITIAL 0
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@ -334,6 +332,7 @@ static twa_message_type twa_error_table[] = {
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#define TW_PHASE_SGLIST 2
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/* Misc defines */
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#define TW_9550SX_DRAIN_COMPLETED 0xFFFF
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#define TW_SECTOR_SIZE 512
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#define TW_ALIGNMENT_9000 4 /* 4 bytes */
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#define TW_ALIGNMENT_9000_SGL 0x3
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@ -417,6 +416,9 @@ static twa_message_type twa_error_table[] = {
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#ifndef PCI_DEVICE_ID_3WARE_9000
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#define PCI_DEVICE_ID_3WARE_9000 0x1002
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#endif
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#ifndef PCI_DEVICE_ID_3WARE_9550SX
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#define PCI_DEVICE_ID_3WARE_9550SX 0x1003
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#endif
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/* Bitmask macros to eliminate bitfields */
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@ -443,6 +445,7 @@ static twa_message_type twa_error_table[] = {
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#define TW_STATUS_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0x4)
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#define TW_COMMAND_QUEUE_REG_ADDR(x) (sizeof(dma_addr_t) > 4 ? ((unsigned char __iomem *)x->base_addr + 0x20) : ((unsigned char __iomem *)x->base_addr + 0x8))
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#define TW_RESPONSE_QUEUE_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0xC)
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#define TW_RESPONSE_QUEUE_REG_ADDR_LARGE(x) ((unsigned char __iomem *)x->base_addr + 0x30)
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#define TW_CLEAR_ALL_INTERRUPTS(x) (writel(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
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#define TW_CLEAR_ATTENTION_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
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#define TW_CLEAR_HOST_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
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