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video: exynos_dp: Get pll lock before pattern set

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According to the exynos datasheet (Figure 49-10), we should wait for PLL
lock before programming the training pattern when doing software eDP
link training.

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
This commit is contained in:
Sean Paul 2012-10-31 23:21:00 +00:00 committed by Jingoo Han
parent fadec4b7e5
commit 49ce41f38b
1 changed files with 13 additions and 1 deletions
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14
drivers/video/exynos/exynos_dp_core.c
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@ -265,7 +265,7 @@ static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
static int exynos_dp_link_start(struct exynos_dp_device *dp)
{
u8 buf[4];
int lane, lane_count, retval;
int lane, lane_count, pll_tries, retval;
lane_count = dp->link_train.lane_count;
@ -298,6 +298,18 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
exynos_dp_set_lane_lane_pre_emphasis(dp,
PRE_EMPHASIS_LEVEL_0, lane);
/* Wait for PLL lock */
pll_tries = 0;
while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
dev_err(dp->dev, "Wait for PLL lock timed out\n");
return -ETIMEDOUT;
}
pll_tries++;
usleep_range(90, 120);
}
/* Set training pattern 1 */
exynos_dp_set_training_pattern(dp, TRAINING_PTN1);