ARM: at91: dt: at91sam9g45 family and board device tree files
Create a new device tree source file for Atmel at91sam9g45 SoC family. The Evaluation Kit at91sam9m10g45ek includes it. This first basic support will be populated as drivers and boards will be converted to device tree. Contains serial, dma and interrupt controllers. The generic board file still takes advantage of platform data for early serial init. As we need a storage media and the NAND flash driver is not converted to DT yet, we keep old initialization for it. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Reviewed-by: Rob Herring <rob.herring@calxeda.com>hifive-unleashed-5.1
Nicolas Ferre
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c3b92c8787
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49fe2ba313
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@ -0,0 +1,106 @@
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/*
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* at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
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* applies to AT91SAM9G45, AT91SAM9M10,
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* AT91SAM9G46, AT91SAM9M11 SoC
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*
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* Copyright (C) 2011 Atmel,
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* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
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*
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* Licensed under GPLv2 or later.
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*/
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/include/ "skeleton.dtsi"
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/ {
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model = "Atmel AT91SAM9G45 family SoC";
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compatible = "atmel,at91sam9g45";
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interrupt-parent = <&aic>;
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aliases {
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serial0 = &dbgu;
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serial1 = &usart0;
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serial2 = &usart1;
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serial3 = &usart2;
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serial4 = &usart3;
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};
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cpus {
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cpu@0 {
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compatible = "arm,arm926ejs";
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};
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};
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memory@70000000 {
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reg = <0x70000000 0x10000000>;
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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aic: interrupt-controller@fffff000 {
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#interrupt-cells = <1>;
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compatible = "atmel,at91rm9200-aic";
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interrupt-controller;
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interrupt-parent;
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reg = <0xfffff000 0x200>;
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};
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dma: dma-controller@ffffec00 {
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compatible = "atmel,at91sam9g45-dma";
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reg = <0xffffec00 0x200>;
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interrupts = <21>;
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};
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dbgu: serial@ffffee00 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xffffee00 0x200>;
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interrupts = <1>;
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status = "disabled";
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};
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usart0: serial@fff8c000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xfff8c000 0x200>;
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interrupts = <7>;
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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};
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usart1: serial@fff90000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xfff90000 0x200>;
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interrupts = <8>;
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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};
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usart2: serial@fff94000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xfff94000 0x200>;
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interrupts = <9>;
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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};
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usart3: serial@fff98000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xfff98000 0x200>;
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interrupts = <10>;
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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};
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};
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};
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};
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@ -0,0 +1,35 @@
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/*
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* at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
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*
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* Copyright (C) 2011 Atmel,
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* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
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*
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* Licensed under GPLv2 or later.
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*/
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/dts-v1/;
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/include/ "at91sam9g45.dtsi"
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/ {
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model = "Atmel AT91SAM9M10G45-EK";
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compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9";
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chosen {
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bootargs = "mem=64M console=ttyS0,115200 mtdparts=atmel_nand:4M(bootstrap/uboot/kernel)ro,60M(rootfs),-(data) root=/dev/mtdblock1 rw rootfstype=jffs2";
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};
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memory@70000000 {
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reg = <0x70000000 0x4000000>;
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};
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ahb {
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apb {
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dbgu: serial@ffffee00 {
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status = "okay";
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};
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usart1: serial@fff90000 {
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status = "okay";
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};
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};
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};
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};
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@ -442,6 +442,17 @@ endif
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# ----------------------------------------------------------
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comment "Generic Board Type"
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config MACH_AT91SAM_DT
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bool "Atmel AT91SAM Evaluation Kits with device-tree support"
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select USE_OF
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help
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Select this if you want to experiment device-tree with
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an Atmel Evaluation Kit.
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# ----------------------------------------------------------
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comment "AT91 Board Options"
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config MTD_AT91_DATAFLASH_CARD
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@ -74,6 +74,9 @@ obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
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# AT91SAM9G45 board-specific support
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obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
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# AT91SAM board with device-tree
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obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o
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# AT91CAP9 board-specific support
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obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o
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@ -16,3 +16,5 @@ else
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params_phys-y := 0x20000100
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initrd_phys-y := 0x20410000
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endif
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dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb
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@ -215,6 +215,12 @@ static struct clk_lookup periph_clocks_lookups[] = {
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CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
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CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
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CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
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/* more usart lookup table for DT entries */
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CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
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CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
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CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
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CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
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CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
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};
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static struct clk_lookup usart_clocks_lookups[] = {
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@ -0,0 +1,122 @@
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/*
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* Setup code for AT91SAM Evaluation Kits with Device Tree support
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*
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* Covers: * AT91SAM9G45-EKES board
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* * AT91SAM9M10-EKES board
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* * AT91SAM9M10G45-EK board
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*
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* Copyright (C) 2011 Atmel,
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* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/gpio.h>
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#include <linux/irqdomain.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <mach/hardware.h>
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#include <mach/board.h>
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#include <mach/system_rev.h>
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#include <mach/at91sam9_smc.h>
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#include <asm/setup.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include "sam9_smc.h"
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#include "generic.h"
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static void __init ek_init_early(void)
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{
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/* Initialize processor: 12.000 MHz crystal */
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at91_initialize(12000000);
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/* DGBU on ttyS0. (Rx & Tx only) */
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at91_register_uart(0, 0, 0);
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/* set serial console to ttyS0 (ie, DBGU) */
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at91_set_serial_console(0);
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}
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/* det_pin is not connected */
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static struct atmel_nand_data __initdata ek_nand_data = {
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.ale = 21,
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.cle = 22,
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.rdy_pin = AT91_PIN_PC8,
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.enable_pin = AT91_PIN_PC14,
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};
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static struct sam9_smc_config __initdata ek_nand_smc_config = {
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.ncs_read_setup = 0,
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.nrd_setup = 2,
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.ncs_write_setup = 0,
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.nwe_setup = 2,
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.ncs_read_pulse = 4,
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.nrd_pulse = 4,
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.ncs_write_pulse = 4,
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.nwe_pulse = 4,
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.read_cycle = 7,
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.write_cycle = 7,
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.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
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.tdf_cycles = 3,
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};
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static void __init ek_add_device_nand(void)
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{
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ek_nand_data.bus_width_16 = board_have_nand_16bit();
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/* setup bus-width (8 or 16) */
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if (ek_nand_data.bus_width_16)
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ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
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else
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ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
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/* configure chip-select 3 (NAND) */
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sam9_smc_configure(3, &ek_nand_smc_config);
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at91_add_device_nand(&ek_nand_data);
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}
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static const struct of_device_id aic_of_match[] __initconst = {
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{ .compatible = "atmel,at91rm9200-aic", },
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{},
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};
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static void __init at91_dt_init_irq(void)
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{
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irq_domain_generate_simple(aic_of_match, 0xfffff000, 0);
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at91_init_irq_default();
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}
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static void __init at91_dt_device_init(void)
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{
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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/* NAND */
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ek_add_device_nand();
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}
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static const char *at91_dt_board_compat[] __initdata = {
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"atmel,at91sam9m10g45ek",
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NULL
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};
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DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
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/* Maintainer: Atmel */
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.timer = &at91sam926x_timer,
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.map_io = at91_map_io,
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.init_early = ek_init_early,
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.init_irq = at91_dt_init_irq,
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.init_machine = at91_dt_device_init,
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.dt_compat = at91_dt_board_compat,
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MACHINE_END
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