bnx2x: registers dump fixes
Fixes in registers dump:
- Properly calculate dump length for 57712.
- Prevent HW blocks parity attentions when dumping registers in order to
prevent false parity errors handling.
- Update the bnx2x_dump.h file: old one had a few bugs that could cause
fatal HW error as a result of a registers dump.
Signed-off-by: Vladislav Zolotarov <vladz@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
hifive-unleashed-5.1
Vladislav Zolotarov
David S. Miller
parent
0744db2394
commit
4a33bc03ab
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@ -636,6 +636,7 @@ struct bnx2x_common {
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#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
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#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
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#define CHIP_PARITY_ENABLED(bp) (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp))
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int flash_size;
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#define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
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File diff suppressed because it is too large
Load Diff
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@ -24,6 +24,7 @@
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#include "bnx2x.h"
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#include "bnx2x_cmn.h"
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#include "bnx2x_dump.h"
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#include "bnx2x_init.h"
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/* Note: in the format strings below %s is replaced by the queue-name which is
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* either its index or 'fcoe' for the fcoe queue. Make sure the format string
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@ -472,7 +473,7 @@ static int bnx2x_get_regs_len(struct net_device *dev)
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{
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struct bnx2x *bp = netdev_priv(dev);
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int regdump_len = 0;
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int i;
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int i, j, k;
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if (CHIP_IS_E1(bp)) {
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for (i = 0; i < REGS_COUNT; i++)
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@ -502,6 +503,15 @@ static int bnx2x_get_regs_len(struct net_device *dev)
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if (IS_E2_ONLINE(wreg_addrs_e2[i].info))
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regdump_len += wreg_addrs_e2[i].size *
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(1 + wreg_addrs_e2[i].read_regs_count);
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for (i = 0; i < PAGE_MODE_VALUES_E2; i++)
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for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
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for (k = 0; k < PAGE_READ_REGS_E2; k++)
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if (IS_E2_ONLINE(page_read_regs_e2[k].
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info))
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regdump_len +=
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page_read_regs_e2[k].size;
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}
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}
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regdump_len *= 4;
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regdump_len += sizeof(struct dump_hdr);
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@ -539,6 +549,12 @@ static void bnx2x_get_regs(struct net_device *dev,
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if (!netif_running(bp->dev))
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return;
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/* Disable parity attentions as long as following dump may
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* cause false alarms by reading never written registers. We
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* will re-enable parity attentions right after the dump.
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*/
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bnx2x_disable_blocks_parity(bp);
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dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
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dump_hdr.dump_sign = dump_sign_all;
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dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
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@ -580,6 +596,10 @@ static void bnx2x_get_regs(struct net_device *dev,
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bnx2x_read_pages_regs_e2(bp, p);
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}
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/* Re-enable parity attentions */
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bnx2x_clear_blocks_parity(bp);
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if (CHIP_PARITY_ENABLED(bp))
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bnx2x_enable_blocks_parity(bp);
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}
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#define PHY_FW_VER_LEN 20
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@ -192,5 +192,225 @@ struct src_ent {
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u64 next;
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};
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/****************************************************************************
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* Parity configuration
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****************************************************************************/
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#define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2) \
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{ \
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block##_REG_##block##_PRTY_MASK, \
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block##_REG_##block##_PRTY_STS_CLR, \
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en_mask, {m1, m1h, m2}, #block \
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}
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#define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2) \
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{ \
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block##_REG_##block##_PRTY_MASK_0, \
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block##_REG_##block##_PRTY_STS_CLR_0, \
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en_mask, {m1, m1h, m2}, #block"_0" \
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}
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#define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2) \
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{ \
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block##_REG_##block##_PRTY_MASK_1, \
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block##_REG_##block##_PRTY_STS_CLR_1, \
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en_mask, {m1, m1h, m2}, #block"_1" \
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}
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static const struct {
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u32 mask_addr;
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u32 sts_clr_addr;
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u32 en_mask; /* Mask to enable parity attentions */
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struct {
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u32 e1; /* 57710 */
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u32 e1h; /* 57711 */
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u32 e2; /* 57712 */
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} reg_mask; /* Register mask (all valid bits) */
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char name[7]; /* Block's longest name is 6 characters long
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* (name + suffix)
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*/
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} bnx2x_blocks_parity_data[] = {
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/* bit 19 masked */
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/* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
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/* bit 5,18,20-31 */
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/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
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/* bit 5 */
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/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
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/* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
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/* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
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/* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
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* want to handle "system kill" flow at the moment.
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*/
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BLOCK_PRTY_INFO(PXP, 0x3ffffff, 0x3ffffff, 0x3ffffff, 0x3ffffff),
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BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff),
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BLOCK_PRTY_INFO_1(PXP2, 0x7ff, 0x7f, 0x7f, 0x7ff),
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BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0),
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BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff),
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BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1),
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BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff),
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BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3),
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{GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
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GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0,
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{0xf, 0xf, 0xf}, "UPB"},
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{GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
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GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
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{0xf, 0xf, 0xf}, "XPB"},
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BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7),
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BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f),
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BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf),
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BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1),
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BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf),
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BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf),
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BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff),
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BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff),
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BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
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BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff),
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BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
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BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
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BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f),
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BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
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BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f),
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BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
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BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f),
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BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
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BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f),
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};
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/* [28] MCP Latched rom_parity
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* [29] MCP Latched ump_rx_parity
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* [30] MCP Latched ump_tx_parity
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* [31] MCP Latched scpad_parity
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*/
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#define MISC_AEU_ENABLE_MCP_PRTY_BITS \
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(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
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/* Below registers control the MCP parity attention output. When
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* MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
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* enabled, when cleared - disabled.
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*/
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static const u32 mcp_attn_ctl_regs[] = {
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MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
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MISC_REG_AEU_ENABLE4_NIG_0,
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MISC_REG_AEU_ENABLE4_PXP_0,
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MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
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MISC_REG_AEU_ENABLE4_NIG_1,
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MISC_REG_AEU_ENABLE4_PXP_1
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};
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static inline void bnx2x_set_mcp_parity(struct bnx2x *bp, u8 enable)
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{
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int i;
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u32 reg_val;
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for (i = 0; i < ARRAY_SIZE(mcp_attn_ctl_regs); i++) {
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reg_val = REG_RD(bp, mcp_attn_ctl_regs[i]);
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if (enable)
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reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS;
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else
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reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS;
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REG_WR(bp, mcp_attn_ctl_regs[i], reg_val);
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}
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}
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static inline u32 bnx2x_parity_reg_mask(struct bnx2x *bp, int idx)
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{
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if (CHIP_IS_E1(bp))
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return bnx2x_blocks_parity_data[idx].reg_mask.e1;
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else if (CHIP_IS_E1H(bp))
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return bnx2x_blocks_parity_data[idx].reg_mask.e1h;
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else
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return bnx2x_blocks_parity_data[idx].reg_mask.e2;
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}
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static inline void bnx2x_disable_blocks_parity(struct bnx2x *bp)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
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u32 dis_mask = bnx2x_parity_reg_mask(bp, i);
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if (dis_mask) {
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REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
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dis_mask);
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DP(NETIF_MSG_HW, "Setting parity mask "
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"for %s to\t\t0x%x\n",
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bnx2x_blocks_parity_data[i].name, dis_mask);
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}
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}
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/* Disable MCP parity attentions */
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bnx2x_set_mcp_parity(bp, false);
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}
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/**
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* Clear the parity error status registers.
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*/
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static inline void bnx2x_clear_blocks_parity(struct bnx2x *bp)
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{
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int i;
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u32 reg_val, mcp_aeu_bits =
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY |
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY;
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/* Clear SEM_FAST parities */
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REG_WR(bp, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
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REG_WR(bp, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
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REG_WR(bp, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
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REG_WR(bp, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
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for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
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u32 reg_mask = bnx2x_parity_reg_mask(bp, i);
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if (reg_mask) {
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reg_val = REG_RD(bp, bnx2x_blocks_parity_data[i].
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sts_clr_addr);
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if (reg_val & reg_mask)
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DP(NETIF_MSG_HW,
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"Parity errors in %s: 0x%x\n",
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bnx2x_blocks_parity_data[i].name,
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reg_val & reg_mask);
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}
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}
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/* Check if there were parity attentions in MCP */
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reg_val = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_MCP);
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if (reg_val & mcp_aeu_bits)
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DP(NETIF_MSG_HW, "Parity error in MCP: 0x%x\n",
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reg_val & mcp_aeu_bits);
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/* Clear parity attentions in MCP:
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* [7] clears Latched rom_parity
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* [8] clears Latched ump_rx_parity
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* [9] clears Latched ump_tx_parity
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* [10] clears Latched scpad_parity (both ports)
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*/
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REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);
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}
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static inline void bnx2x_enable_blocks_parity(struct bnx2x *bp)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
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u32 reg_mask = bnx2x_parity_reg_mask(bp, i);
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if (reg_mask)
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REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
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bnx2x_blocks_parity_data[i].en_mask & reg_mask);
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}
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/* Enable MCP parity attentions */
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bnx2x_set_mcp_parity(bp, true);
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}
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#endif /* BNX2X_INIT_H */
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@ -3152,7 +3152,6 @@ static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
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#define LOAD_COUNTER_MASK (((u32)0x1 << LOAD_COUNTER_BITS) - 1)
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#define RESET_DONE_FLAG_MASK (~LOAD_COUNTER_MASK)
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#define RESET_DONE_FLAG_SHIFT LOAD_COUNTER_BITS
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#define CHIP_PARITY_SUPPORTED(bp) (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp))
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/*
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* should be run under rtnl lock
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@ -3527,7 +3526,7 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
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try to handle this event */
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bnx2x_acquire_alr(bp);
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if (bnx2x_chk_parity_attn(bp)) {
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if (CHIP_PARITY_ENABLED(bp) && bnx2x_chk_parity_attn(bp)) {
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bp->recovery_state = BNX2X_RECOVERY_INIT;
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bnx2x_set_reset_in_progress(bp);
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schedule_delayed_work(&bp->reset_task, 0);
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@ -4754,7 +4753,7 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
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return 0; /* OK */
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}
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static void enable_blocks_attention(struct bnx2x *bp)
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static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
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{
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REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
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if (CHIP_IS_E2(bp))
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@ -4808,53 +4807,9 @@ static void enable_blocks_attention(struct bnx2x *bp)
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REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
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REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
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/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
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REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18); /* bit 3,4 masked */
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REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
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}
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static const struct {
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u32 addr;
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u32 mask;
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} bnx2x_parity_mask[] = {
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{PXP_REG_PXP_PRTY_MASK, 0x3ffffff},
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{PXP2_REG_PXP2_PRTY_MASK_0, 0xffffffff},
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{PXP2_REG_PXP2_PRTY_MASK_1, 0x7f},
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{HC_REG_HC_PRTY_MASK, 0x7},
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{MISC_REG_MISC_PRTY_MASK, 0x1},
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{QM_REG_QM_PRTY_MASK, 0x0},
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{DORQ_REG_DORQ_PRTY_MASK, 0x0},
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{GRCBASE_UPB + PB_REG_PB_PRTY_MASK, 0x0},
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{GRCBASE_XPB + PB_REG_PB_PRTY_MASK, 0x0},
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{SRC_REG_SRC_PRTY_MASK, 0x4}, /* bit 2 */
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{CDU_REG_CDU_PRTY_MASK, 0x0},
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{CFC_REG_CFC_PRTY_MASK, 0x0},
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{DBG_REG_DBG_PRTY_MASK, 0x0},
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{DMAE_REG_DMAE_PRTY_MASK, 0x0},
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{BRB1_REG_BRB1_PRTY_MASK, 0x0},
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{PRS_REG_PRS_PRTY_MASK, (1<<6)},/* bit 6 */
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{TSDM_REG_TSDM_PRTY_MASK, 0x18}, /* bit 3,4 */
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{CSDM_REG_CSDM_PRTY_MASK, 0x8}, /* bit 3 */
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{USDM_REG_USDM_PRTY_MASK, 0x38}, /* bit 3,4,5 */
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||||
{XSDM_REG_XSDM_PRTY_MASK, 0x8}, /* bit 3 */
|
||||
{TSEM_REG_TSEM_PRTY_MASK_0, 0x0},
|
||||
{TSEM_REG_TSEM_PRTY_MASK_1, 0x0},
|
||||
{USEM_REG_USEM_PRTY_MASK_0, 0x0},
|
||||
{USEM_REG_USEM_PRTY_MASK_1, 0x0},
|
||||
{CSEM_REG_CSEM_PRTY_MASK_0, 0x0},
|
||||
{CSEM_REG_CSEM_PRTY_MASK_1, 0x0},
|
||||
{XSEM_REG_XSEM_PRTY_MASK_0, 0x0},
|
||||
{XSEM_REG_XSEM_PRTY_MASK_1, 0x0}
|
||||
};
|
||||
|
||||
static void enable_blocks_parity(struct bnx2x *bp)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(bnx2x_parity_mask); i++)
|
||||
REG_WR(bp, bnx2x_parity_mask[i].addr,
|
||||
bnx2x_parity_mask[i].mask);
|
||||
}
|
||||
|
||||
|
||||
static void bnx2x_reset_common(struct bnx2x *bp)
|
||||
{
|
||||
/* reset_common */
|
||||
|
|
@ -5350,9 +5305,9 @@ static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
|
|||
/* clear PXP2 attentions */
|
||||
REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
|
||||
|
||||
enable_blocks_attention(bp);
|
||||
if (CHIP_PARITY_SUPPORTED(bp))
|
||||
enable_blocks_parity(bp);
|
||||
bnx2x_enable_blocks_attention(bp);
|
||||
if (CHIP_PARITY_ENABLED(bp))
|
||||
bnx2x_enable_blocks_parity(bp);
|
||||
|
||||
if (!BP_NOMCP(bp)) {
|
||||
/* In E2 2-PORT mode, same ext phy is used for the two paths */
|
||||
|
|
|
|||
|
|
@ -18,6 +18,8 @@
|
|||
* WR - Write Clear (write 1 to clear the bit)
|
||||
*
|
||||
*/
|
||||
#ifndef BNX2X_REG_H
|
||||
#define BNX2X_REG_H
|
||||
|
||||
#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
|
||||
#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
|
||||
|
|
@ -39,6 +41,8 @@
|
|||
#define BRB1_REG_BRB1_PRTY_MASK 0x60138
|
||||
/* [R 4] Parity register #0 read */
|
||||
#define BRB1_REG_BRB1_PRTY_STS 0x6012c
|
||||
/* [RC 4] Parity register #0 read clear */
|
||||
#define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130
|
||||
/* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
|
||||
* address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
|
||||
* BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
|
||||
|
|
@ -132,8 +136,12 @@
|
|||
#define CCM_REG_CCM_INT_MASK 0xd01e4
|
||||
/* [R 11] Interrupt register #0 read */
|
||||
#define CCM_REG_CCM_INT_STS 0xd01d8
|
||||
/* [RW 27] Parity mask register #0 read/write */
|
||||
#define CCM_REG_CCM_PRTY_MASK 0xd01f4
|
||||
/* [R 27] Parity register #0 read */
|
||||
#define CCM_REG_CCM_PRTY_STS 0xd01e8
|
||||
/* [RC 27] Parity register #0 read clear */
|
||||
#define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec
|
||||
/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
|
||||
REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
|
||||
Is used to determine the number of the AG context REG-pairs written back;
|
||||
|
|
@ -350,6 +358,8 @@
|
|||
#define CDU_REG_CDU_PRTY_MASK 0x10104c
|
||||
/* [R 5] Parity register #0 read */
|
||||
#define CDU_REG_CDU_PRTY_STS 0x101040
|
||||
/* [RC 5] Parity register #0 read clear */
|
||||
#define CDU_REG_CDU_PRTY_STS_CLR 0x101044
|
||||
/* [RC 32] logging of error data in case of a CDU load error:
|
||||
{expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
|
||||
ype_error; ctual_active; ctual_compressed_context}; */
|
||||
|
|
@ -381,6 +391,8 @@
|
|||
#define CFC_REG_CFC_PRTY_MASK 0x104118
|
||||
/* [R 4] Parity register #0 read */
|
||||
#define CFC_REG_CFC_PRTY_STS 0x10410c
|
||||
/* [RC 4] Parity register #0 read clear */
|
||||
#define CFC_REG_CFC_PRTY_STS_CLR 0x104110
|
||||
/* [RW 21] CID cam access (21:1 - Data; alid - 0) */
|
||||
#define CFC_REG_CID_CAM 0x104800
|
||||
#define CFC_REG_CONTROL0 0x104028
|
||||
|
|
@ -466,6 +478,8 @@
|
|||
#define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
|
||||
/* [R 11] Parity register #0 read */
|
||||
#define CSDM_REG_CSDM_PRTY_STS 0xc22b0
|
||||
/* [RC 11] Parity register #0 read clear */
|
||||
#define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4
|
||||
#define CSDM_REG_ENABLE_IN1 0xc2238
|
||||
#define CSDM_REG_ENABLE_IN2 0xc223c
|
||||
#define CSDM_REG_ENABLE_OUT1 0xc2240
|
||||
|
|
@ -556,6 +570,9 @@
|
|||
/* [R 32] Parity register #0 read */
|
||||
#define CSEM_REG_CSEM_PRTY_STS_0 0x200124
|
||||
#define CSEM_REG_CSEM_PRTY_STS_1 0x200134
|
||||
/* [RC 32] Parity register #0 read clear */
|
||||
#define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128
|
||||
#define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138
|
||||
#define CSEM_REG_ENABLE_IN 0x2000a4
|
||||
#define CSEM_REG_ENABLE_OUT 0x2000a8
|
||||
/* [RW 32] This address space contains all registers and memories that are
|
||||
|
|
@ -648,6 +665,8 @@
|
|||
#define DBG_REG_DBG_PRTY_MASK 0xc0a8
|
||||
/* [R 1] Parity register #0 read */
|
||||
#define DBG_REG_DBG_PRTY_STS 0xc09c
|
||||
/* [RC 1] Parity register #0 read clear */
|
||||
#define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0
|
||||
/* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The
|
||||
* function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0;
|
||||
* 4.Completion function=0; 5.Error handling=0 */
|
||||
|
|
@ -668,6 +687,8 @@
|
|||
#define DMAE_REG_DMAE_PRTY_MASK 0x102064
|
||||
/* [R 4] Parity register #0 read */
|
||||
#define DMAE_REG_DMAE_PRTY_STS 0x102058
|
||||
/* [RC 4] Parity register #0 read clear */
|
||||
#define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c
|
||||
/* [RW 1] Command 0 go. */
|
||||
#define DMAE_REG_GO_C0 0x102080
|
||||
/* [RW 1] Command 1 go. */
|
||||
|
|
@ -734,6 +755,8 @@
|
|||
#define DORQ_REG_DORQ_PRTY_MASK 0x170190
|
||||
/* [R 2] Parity register #0 read */
|
||||
#define DORQ_REG_DORQ_PRTY_STS 0x170184
|
||||
/* [RC 2] Parity register #0 read clear */
|
||||
#define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188
|
||||
/* [RW 8] The address to write the DPM CID to STORM. */
|
||||
#define DORQ_REG_DPM_CID_ADDR 0x170044
|
||||
/* [RW 5] The DPM mode CID extraction offset. */
|
||||
|
|
@ -842,8 +865,12 @@
|
|||
/* [R 1] data availble for error memory. If this bit is clear do not red
|
||||
* from error_handling_memory. */
|
||||
#define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130
|
||||
/* [RW 11] Parity mask register #0 read/write */
|
||||
#define IGU_REG_IGU_PRTY_MASK 0x1300a8
|
||||
/* [R 11] Parity register #0 read */
|
||||
#define IGU_REG_IGU_PRTY_STS 0x13009c
|
||||
/* [RC 11] Parity register #0 read clear */
|
||||
#define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0
|
||||
/* [R 4] Debug: int_handle_fsm */
|
||||
#define IGU_REG_INT_HANDLE_FSM 0x130050
|
||||
#define IGU_REG_LEADING_EDGE_LATCH 0x130134
|
||||
|
|
@ -1501,6 +1528,8 @@
|
|||
#define MISC_REG_MISC_PRTY_MASK 0xa398
|
||||
/* [R 1] Parity register #0 read */
|
||||
#define MISC_REG_MISC_PRTY_STS 0xa38c
|
||||
/* [RC 1] Parity register #0 read clear */
|
||||
#define MISC_REG_MISC_PRTY_STS_CLR 0xa390
|
||||
#define MISC_REG_NIG_WOL_P0 0xa270
|
||||
#define MISC_REG_NIG_WOL_P1 0xa274
|
||||
/* [R 1] If set indicate that the pcie_rst_b was asserted without perst
|
||||
|
|
@ -2082,6 +2111,10 @@
|
|||
#define PBF_REG_PBF_INT_MASK 0x1401d4
|
||||
/* [R 5] Interrupt register #0 read */
|
||||
#define PBF_REG_PBF_INT_STS 0x1401c8
|
||||
/* [RW 20] Parity mask register #0 read/write */
|
||||
#define PBF_REG_PBF_PRTY_MASK 0x1401e4
|
||||
/* [RC 20] Parity register #0 read clear */
|
||||
#define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc
|
||||
#define PB_REG_CONTROL 0
|
||||
/* [RW 2] Interrupt mask register #0 read/write */
|
||||
#define PB_REG_PB_INT_MASK 0x28
|
||||
|
|
@ -2091,6 +2124,8 @@
|
|||
#define PB_REG_PB_PRTY_MASK 0x38
|
||||
/* [R 4] Parity register #0 read */
|
||||
#define PB_REG_PB_PRTY_STS 0x2c
|
||||
/* [RC 4] Parity register #0 read clear */
|
||||
#define PB_REG_PB_PRTY_STS_CLR 0x30
|
||||
#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
|
||||
#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)
|
||||
#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)
|
||||
|
|
@ -2446,6 +2481,8 @@
|
|||
#define PRS_REG_PRS_PRTY_MASK 0x401a4
|
||||
/* [R 8] Parity register #0 read */
|
||||
#define PRS_REG_PRS_PRTY_STS 0x40198
|
||||
/* [RC 8] Parity register #0 read clear */
|
||||
#define PRS_REG_PRS_PRTY_STS_CLR 0x4019c
|
||||
/* [RW 8] Context region for pure acknowledge packets. Used in CFC load
|
||||
request message */
|
||||
#define PRS_REG_PURE_REGIONS 0x40024
|
||||
|
|
@ -2599,6 +2636,9 @@
|
|||
/* [R 32] Parity register #0 read */
|
||||
#define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
|
||||
#define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
|
||||
/* [RC 32] Parity register #0 read clear */
|
||||
#define PXP2_REG_PXP2_PRTY_STS_CLR_0 0x120580
|
||||
#define PXP2_REG_PXP2_PRTY_STS_CLR_1 0x120590
|
||||
/* [R 1] Debug only: The 'almost full' indication from each fifo (gives
|
||||
indication about backpressure) */
|
||||
#define PXP2_REG_RD_ALMOST_FULL_0 0x120424
|
||||
|
|
@ -3001,6 +3041,8 @@
|
|||
#define PXP_REG_PXP_PRTY_MASK 0x103094
|
||||
/* [R 26] Parity register #0 read */
|
||||
#define PXP_REG_PXP_PRTY_STS 0x103088
|
||||
/* [RC 27] Parity register #0 read clear */
|
||||
#define PXP_REG_PXP_PRTY_STS_CLR 0x10308c
|
||||
/* [RW 4] The activity counter initial increment value sent in the load
|
||||
request */
|
||||
#define QM_REG_ACTCTRINITVAL_0 0x168040
|
||||
|
|
@ -3157,6 +3199,8 @@
|
|||
#define QM_REG_QM_PRTY_MASK 0x168454
|
||||
/* [R 12] Parity register #0 read */
|
||||
#define QM_REG_QM_PRTY_STS 0x168448
|
||||
/* [RC 12] Parity register #0 read clear */
|
||||
#define QM_REG_QM_PRTY_STS_CLR 0x16844c
|
||||
/* [R 32] Current queues in pipeline: Queues from 32 to 63 */
|
||||
#define QM_REG_QSTATUS_HIGH 0x16802c
|
||||
/* [R 32] Current queues in pipeline: Queues from 96 to 127 */
|
||||
|
|
@ -3442,6 +3486,8 @@
|
|||
#define QM_REG_WRRWEIGHTS_9 0x168848
|
||||
/* [R 6] Keep the fill level of the fifo from write client 1 */
|
||||
#define QM_REG_XQM_WRC_FIFOLVL 0x168000
|
||||
/* [W 1] reset to parity interrupt */
|
||||
#define SEM_FAST_REG_PARITY_RST 0x18840
|
||||
#define SRC_REG_COUNTFREE0 0x40500
|
||||
/* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
|
||||
ports. If set the searcher support 8 functions. */
|
||||
|
|
@ -3470,6 +3516,8 @@
|
|||
#define SRC_REG_SRC_PRTY_MASK 0x404c8
|
||||
/* [R 3] Parity register #0 read */
|
||||
#define SRC_REG_SRC_PRTY_STS 0x404bc
|
||||
/* [RC 3] Parity register #0 read clear */
|
||||
#define SRC_REG_SRC_PRTY_STS_CLR 0x404c0
|
||||
/* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
|
||||
#define TCM_REG_CAM_OCCUP 0x5017c
|
||||
/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
|
||||
|
|
@ -3596,8 +3644,12 @@
|
|||
#define TCM_REG_TCM_INT_MASK 0x501dc
|
||||
/* [R 11] Interrupt register #0 read */
|
||||
#define TCM_REG_TCM_INT_STS 0x501d0
|
||||
/* [RW 27] Parity mask register #0 read/write */
|
||||
#define TCM_REG_TCM_PRTY_MASK 0x501ec
|
||||
/* [R 27] Parity register #0 read */
|
||||
#define TCM_REG_TCM_PRTY_STS 0x501e0
|
||||
/* [RC 27] Parity register #0 read clear */
|
||||
#define TCM_REG_TCM_PRTY_STS_CLR 0x501e4
|
||||
/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
|
||||
REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
|
||||
Is used to determine the number of the AG context REG-pairs written back;
|
||||
|
|
@ -3755,6 +3807,10 @@
|
|||
#define TM_REG_TM_INT_MASK 0x1640fc
|
||||
/* [R 1] Interrupt register #0 read */
|
||||
#define TM_REG_TM_INT_STS 0x1640f0
|
||||
/* [RW 7] Parity mask register #0 read/write */
|
||||
#define TM_REG_TM_PRTY_MASK 0x16410c
|
||||
/* [RC 7] Parity register #0 read clear */
|
||||
#define TM_REG_TM_PRTY_STS_CLR 0x164104
|
||||
/* [RW 8] The event id for aggregated interrupt 0 */
|
||||
#define TSDM_REG_AGG_INT_EVENT_0 0x42038
|
||||
#define TSDM_REG_AGG_INT_EVENT_1 0x4203c
|
||||
|
|
@ -3835,6 +3891,8 @@
|
|||
#define TSDM_REG_TSDM_PRTY_MASK 0x422bc
|
||||
/* [R 11] Parity register #0 read */
|
||||
#define TSDM_REG_TSDM_PRTY_STS 0x422b0
|
||||
/* [RC 11] Parity register #0 read clear */
|
||||
#define TSDM_REG_TSDM_PRTY_STS_CLR 0x422b4
|
||||
/* [RW 5] The number of time_slots in the arbitration cycle */
|
||||
#define TSEM_REG_ARB_CYCLE_SIZE 0x180034
|
||||
/* [RW 3] The source that is associated with arbitration element 0. Source
|
||||
|
|
@ -3914,6 +3972,9 @@
|
|||
#define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
|
||||
/* [RW 8] List of free threads . There is a bit per thread. */
|
||||
#define TSEM_REG_THREADS_LIST 0x1802e4
|
||||
/* [RC 32] Parity register #0 read clear */
|
||||
#define TSEM_REG_TSEM_PRTY_STS_CLR_0 0x180118
|
||||
#define TSEM_REG_TSEM_PRTY_STS_CLR_1 0x180128
|
||||
/* [RW 3] The arbitration scheme of time_slot 0 */
|
||||
#define TSEM_REG_TS_0_AS 0x180038
|
||||
/* [RW 3] The arbitration scheme of time_slot 10 */
|
||||
|
|
@ -4116,6 +4177,8 @@
|
|||
#define UCM_REG_UCM_INT_STS 0xe01c8
|
||||
/* [R 27] Parity register #0 read */
|
||||
#define UCM_REG_UCM_PRTY_STS 0xe01d8
|
||||
/* [RC 27] Parity register #0 read clear */
|
||||
#define UCM_REG_UCM_PRTY_STS_CLR 0xe01dc
|
||||
/* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
|
||||
REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
|
||||
Is used to determine the number of the AG context REG-pairs written back;
|
||||
|
|
@ -4292,6 +4355,8 @@
|
|||
#define USDM_REG_USDM_PRTY_MASK 0xc42c0
|
||||
/* [R 11] Parity register #0 read */
|
||||
#define USDM_REG_USDM_PRTY_STS 0xc42b4
|
||||
/* [RC 11] Parity register #0 read clear */
|
||||
#define USDM_REG_USDM_PRTY_STS_CLR 0xc42b8
|
||||
/* [RW 5] The number of time_slots in the arbitration cycle */
|
||||
#define USEM_REG_ARB_CYCLE_SIZE 0x300034
|
||||
/* [RW 3] The source that is associated with arbitration element 0. Source
|
||||
|
|
@ -4421,6 +4486,9 @@
|
|||
/* [R 32] Parity register #0 read */
|
||||
#define USEM_REG_USEM_PRTY_STS_0 0x300124
|
||||
#define USEM_REG_USEM_PRTY_STS_1 0x300134
|
||||
/* [RC 32] Parity register #0 read clear */
|
||||
#define USEM_REG_USEM_PRTY_STS_CLR_0 0x300128
|
||||
#define USEM_REG_USEM_PRTY_STS_CLR_1 0x300138
|
||||
/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
|
||||
* VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
|
||||
#define USEM_REG_VFPF_ERR_NUM 0x300380
|
||||
|
|
@ -4797,6 +4865,8 @@
|
|||
#define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
|
||||
/* [R 11] Parity register #0 read */
|
||||
#define XSDM_REG_XSDM_PRTY_STS 0x1662b0
|
||||
/* [RC 11] Parity register #0 read clear */
|
||||
#define XSDM_REG_XSDM_PRTY_STS_CLR 0x1662b4
|
||||
/* [RW 5] The number of time_slots in the arbitration cycle */
|
||||
#define XSEM_REG_ARB_CYCLE_SIZE 0x280034
|
||||
/* [RW 3] The source that is associated with arbitration element 0. Source
|
||||
|
|
@ -4929,6 +4999,9 @@
|
|||
/* [R 32] Parity register #0 read */
|
||||
#define XSEM_REG_XSEM_PRTY_STS_0 0x280124
|
||||
#define XSEM_REG_XSEM_PRTY_STS_1 0x280134
|
||||
/* [RC 32] Parity register #0 read clear */
|
||||
#define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x280128
|
||||
#define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x280138
|
||||
#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
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#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
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#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
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@ -6316,3 +6389,4 @@ static inline u8 calc_crc8(u32 data, u8 crc)
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}
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||||
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#endif /* BNX2X_REG_H */
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||||
|
|
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Loading…
Reference in New Issue