drm/radeon: implement pci config reset for SI (v2)
pci config reset is a low level reset that resets the entire chip from the bus interface. It can be more reliable if soft reset fails. v2: hide behind module parameter Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
b5470b036e
commit
4a5c8ea59f
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@ -80,6 +80,8 @@ extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
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extern bool evergreen_is_display_hung(struct radeon_device *rdev);
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static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
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bool enable);
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static void si_init_pg(struct radeon_device *rdev);
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static void si_init_cg(struct radeon_device *rdev);
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static void si_fini_pg(struct radeon_device *rdev);
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static void si_fini_cg(struct radeon_device *rdev);
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static void si_rlc_stop(struct radeon_device *rdev);
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@ -3722,6 +3724,106 @@ static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
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evergreen_print_gpu_status_regs(rdev);
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}
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static void si_set_clk_bypass_mode(struct radeon_device *rdev)
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{
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u32 tmp, i;
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tmp = RREG32(CG_SPLL_FUNC_CNTL);
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tmp |= SPLL_BYPASS_EN;
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WREG32(CG_SPLL_FUNC_CNTL, tmp);
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tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
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tmp |= SPLL_CTLREQ_CHG;
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WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
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for (i = 0; i < rdev->usec_timeout; i++) {
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if (RREG32(SPLL_STATUS) & SPLL_CHG_STATUS)
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break;
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udelay(1);
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}
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tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
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tmp &= ~(SPLL_CTLREQ_CHG | SCLK_MUX_UPDATE);
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WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
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tmp = RREG32(MPLL_CNTL_MODE);
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tmp &= ~MPLL_MCLK_SEL;
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WREG32(MPLL_CNTL_MODE, tmp);
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}
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static void si_spll_powerdown(struct radeon_device *rdev)
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{
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u32 tmp;
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tmp = RREG32(SPLL_CNTL_MODE);
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tmp |= SPLL_SW_DIR_CONTROL;
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WREG32(SPLL_CNTL_MODE, tmp);
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tmp = RREG32(CG_SPLL_FUNC_CNTL);
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tmp |= SPLL_RESET;
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WREG32(CG_SPLL_FUNC_CNTL, tmp);
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tmp = RREG32(CG_SPLL_FUNC_CNTL);
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tmp |= SPLL_SLEEP;
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WREG32(CG_SPLL_FUNC_CNTL, tmp);
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tmp = RREG32(SPLL_CNTL_MODE);
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tmp &= ~SPLL_SW_DIR_CONTROL;
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WREG32(SPLL_CNTL_MODE, tmp);
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}
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static void si_gpu_pci_config_reset(struct radeon_device *rdev)
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{
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struct evergreen_mc_save save;
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u32 tmp, i;
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dev_info(rdev->dev, "GPU pci config reset\n");
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/* disable dpm? */
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/* disable cg/pg */
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si_fini_pg(rdev);
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si_fini_cg(rdev);
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/* Disable CP parsing/prefetching */
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WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
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/* dma0 */
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tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
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tmp &= ~DMA_RB_ENABLE;
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WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
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/* dma1 */
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tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
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tmp &= ~DMA_RB_ENABLE;
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WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
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/* XXX other engines? */
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/* halt the rlc, disable cp internal ints */
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si_rlc_stop(rdev);
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udelay(50);
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/* disable mem access */
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evergreen_mc_stop(rdev, &save);
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if (evergreen_mc_wait_for_idle(rdev)) {
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dev_warn(rdev->dev, "Wait for MC idle timed out !\n");
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}
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/* set mclk/sclk to bypass */
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si_set_clk_bypass_mode(rdev);
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/* powerdown spll */
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si_spll_powerdown(rdev);
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/* disable BM */
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pci_clear_master(rdev->pdev);
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/* reset */
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radeon_pci_config_reset(rdev);
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/* wait for asic to come out of reset */
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for (i = 0; i < rdev->usec_timeout; i++) {
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if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
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break;
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udelay(1);
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}
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}
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int si_asic_reset(struct radeon_device *rdev)
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{
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u32 reset_mask;
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@ -3731,10 +3833,17 @@ int si_asic_reset(struct radeon_device *rdev)
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if (reset_mask)
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r600_set_bios_scratch_engine_hung(rdev, true);
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/* try soft reset */
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si_gpu_soft_reset(rdev, reset_mask);
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reset_mask = si_gpu_check_soft_reset(rdev);
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/* try pci config reset */
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if (reset_mask && radeon_hard_reset)
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si_gpu_pci_config_reset(rdev);
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reset_mask = si_gpu_check_soft_reset(rdev);
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if (!reset_mask)
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r600_set_bios_scratch_engine_hung(rdev, false);
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@ -94,6 +94,8 @@
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#define CG_SPLL_FUNC_CNTL_2 0x604
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#define SCLK_MUX_SEL(x) ((x) << 0)
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#define SCLK_MUX_SEL_MASK (0x1ff << 0)
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#define SPLL_CTLREQ_CHG (1 << 23)
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#define SCLK_MUX_UPDATE (1 << 26)
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#define CG_SPLL_FUNC_CNTL_3 0x608
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#define SPLL_FB_DIV(x) ((x) << 0)
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#define SPLL_FB_DIV_MASK (0x3ffffff << 0)
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@ -101,7 +103,10 @@
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#define SPLL_DITHEN (1 << 28)
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#define CG_SPLL_FUNC_CNTL_4 0x60c
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#define SPLL_STATUS 0x614
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#define SPLL_CHG_STATUS (1 << 1)
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#define SPLL_CNTL_MODE 0x618
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#define SPLL_SW_DIR_CONTROL (1 << 0)
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# define SPLL_REFCLK_SEL(x) ((x) << 8)
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# define SPLL_REFCLK_SEL_MASK 0xFF00
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@ -559,6 +564,8 @@
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# define MRDCK0_BYPASS (1 << 24)
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# define MRDCK1_BYPASS (1 << 25)
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#define MPLL_CNTL_MODE 0x2bb0
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# define MPLL_MCLK_SEL (1 << 11)
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#define MPLL_FUNC_CNTL 0x2bb4
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#define BWCTRL(x) ((x) << 20)
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#define BWCTRL_MASK (0xff << 20)
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