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clk: samsung: Fix CLK_SMMU_FIMCL3 clock name on Exynos542x 

The proper name for CLK_SMMU_FIMCL3 is "smmu_fimcl3". Remove obvious
typo.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
alistair/sunxi64-5.8
Marek Szyprowski 2020-05-06 15:26:59 +02:00 committed by Sylwester Nawrocki
parent e47bd937e6
commit 4b159cf13a
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/samsung/clk-exynos5420.c
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@ -1165,7 +1165,7 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
CLK_IS_CRITICAL, 0),
GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13,
CLK_IS_CRITICAL, 0),
GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333",
GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3", "dout_gscl_blk_333",
GATE_IP_GSCL1, 16, 0, 0),
GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
GATE_IP_GSCL1, 17, 0, 0),