imxmmc: Checkpatch cleanup
This cleans up the warnings issued by the checkpatch script and remove the file history from the header Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>hifive-unleashed-5.1
Marc Kleine-Budde
Sascha Hauer
parent
3287abbd71
commit
4b7c0e4cae
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@ -10,20 +10,6 @@
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* 2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz>
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* Changed to conform redesigned i.MX scatter gather DMA interface
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*
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* 2005-11-04 Pavel Pisa <pisa@cmp.felk.cvut.cz>
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* Updated for 2.6.14 kernel
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*
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* 2005-12-13 Jay Monkman <jtm@smoothsmoothie.com>
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* Found and corrected problems in the write path
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*
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* 2005-12-30 Pavel Pisa <pisa@cmp.felk.cvut.cz>
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* The event handling rewritten right way in softirq.
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* Added many ugly hacks and delays to overcome SDHC
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* deficiencies
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*
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*/
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#include <linux/module.h>
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@ -37,9 +23,9 @@
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#include <linux/mmc/card.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <asm/dma.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/sizes.h>
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#include <mach/mmc.h>
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@ -50,8 +36,8 @@
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#define DRIVER_NAME "imx-mmc"
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#define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \
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INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
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INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
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INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
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INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
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struct imxmci_host {
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struct mmc_host *mmc;
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@ -74,7 +60,7 @@ struct imxmci_host {
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struct tasklet_struct tasklet;
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unsigned int status_reg;
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unsigned long pending_events;
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/* Next to fields are there for CPU driven transfers to overcome SDHC deficiencies */
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/* Next two fields are there for CPU driven transfers to overcome SDHC deficiencies */
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u16 *data_ptr;
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unsigned int data_cnt;
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atomic_t stuck_timeout;
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@ -115,13 +101,13 @@ static void imxmci_stop_clock(struct imxmci_host *host)
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{
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int i = 0;
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MMC_STR_STP_CLK &= ~STR_STP_CLK_START_CLK;
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while(i < 0x1000) {
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if(!(i & 0x7f))
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while (i < 0x1000) {
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if (!(i & 0x7f))
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MMC_STR_STP_CLK |= STR_STP_CLK_STOP_CLK;
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if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) {
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if (!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) {
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/* Check twice before cut */
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if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN))
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if (!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN))
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return;
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}
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@ -150,13 +136,13 @@ static int imxmci_start_clock(struct imxmci_host *host)
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do {
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unsigned int delay = delay_limit;
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while(delay--){
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if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
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while (delay--) {
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if (MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
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/* Check twice before cut */
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if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
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if (MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
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return 0;
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if(test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
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if (test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
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return 0;
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}
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@ -167,11 +153,11 @@ static int imxmci_start_clock(struct imxmci_host *host)
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* IRQ or schedule delays this function execution and the clocks has
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* been already stopped by other means (response processing, SDHC HW)
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*/
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if(!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
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if (!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
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MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
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local_irq_restore(flags);
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} while(++trials<256);
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} while (++trials < 256);
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dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n");
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@ -198,13 +184,14 @@ static void imxmci_softreset(void)
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}
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static int imxmci_busy_wait_for_status(struct imxmci_host *host,
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unsigned int *pstat, unsigned int stat_mask,
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int timeout, const char *where)
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unsigned int *pstat, unsigned int stat_mask,
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int timeout, const char *where)
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{
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int loops=0;
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while(!(*pstat & stat_mask)) {
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loops+=2;
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if(loops >= timeout) {
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int loops = 0;
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while (!(*pstat & stat_mask)) {
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loops += 2;
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if (loops >= timeout) {
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dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n",
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where, *pstat, stat_mask);
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return -1;
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@ -212,13 +199,13 @@ static int imxmci_busy_wait_for_status(struct imxmci_host *host,
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udelay(2);
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*pstat |= MMC_STATUS;
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}
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if(!loops)
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if (!loops)
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return 0;
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/* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */
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if(!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock>=8000000))
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if (!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock >= 8000000))
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dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
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loops, where, *pstat, stat_mask);
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loops, where, *pstat, stat_mask);
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return loops;
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}
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@ -259,7 +246,7 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
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}
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/* Convert back to virtual address */
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host->data_ptr = (u16*)sg_virt(data->sg);
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host->data_ptr = (u16 *)sg_virt(data->sg);
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host->data_cnt = 0;
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clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
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@ -271,10 +258,10 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
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if (data->flags & MMC_DATA_READ) {
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host->dma_dir = DMA_FROM_DEVICE;
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host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
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data->sg_len, host->dma_dir);
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data->sg_len, host->dma_dir);
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imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
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host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_READ);
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host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_READ);
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/*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/
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CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN;
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@ -282,10 +269,10 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
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host->dma_dir = DMA_TO_DEVICE;
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host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
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data->sg_len, host->dma_dir);
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data->sg_len, host->dma_dir);
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imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
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host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_WRITE);
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host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_WRITE);
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/*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/
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CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN;
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@ -293,12 +280,12 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
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#if 1 /* This code is there only for consistency checking and can be disabled in future */
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host->dma_size = 0;
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for(i=0; i<host->dma_nents; i++)
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host->dma_size+=data->sg[i].length;
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for (i = 0; i < host->dma_nents; i++)
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host->dma_size += data->sg[i].length;
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if (datasz > host->dma_size) {
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dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n",
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datasz, host->dma_size);
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datasz, host->dma_size);
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}
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#endif
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@ -306,7 +293,7 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
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wmb();
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if(host->actual_bus_width == MMC_BUS_WIDTH_4)
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if (host->actual_bus_width == MMC_BUS_WIDTH_4)
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BLR(host->dma) = 0; /* burst 64 byte read / 64 bytes write */
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else
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BLR(host->dma) = 16; /* burst 16 byte read / 16 bytes write */
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@ -317,9 +304,8 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
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clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
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/* start DMA engine for read, write is delayed after initial response */
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if (host->dma_dir == DMA_FROM_DEVICE) {
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if (host->dma_dir == DMA_FROM_DEVICE)
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imx_dma_enable(host->dma);
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}
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}
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static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat)
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@ -351,10 +337,10 @@ static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd,
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break;
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}
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if ( test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events) )
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if (test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events))
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cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */
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if ( host->actual_bus_width == MMC_BUS_WIDTH_4 )
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if (host->actual_bus_width == MMC_BUS_WIDTH_4)
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cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
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MMC_CMD = cmd->opcode;
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@ -368,12 +354,12 @@ static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd,
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imask = IMXMCI_INT_MASK_DEFAULT;
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imask &= ~INT_MASK_END_CMD_RES;
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if ( cmdat & CMD_DAT_CONT_DATA_ENABLE ) {
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/*imask &= ~INT_MASK_BUF_READY;*/
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if (cmdat & CMD_DAT_CONT_DATA_ENABLE) {
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/* imask &= ~INT_MASK_BUF_READY; */
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imask &= ~INT_MASK_DATA_TRAN;
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if ( cmdat & CMD_DAT_CONT_WRITE )
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if (cmdat & CMD_DAT_CONT_WRITE)
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imask &= ~INT_MASK_WRITE_OP_DONE;
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if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
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if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
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imask &= ~INT_MASK_BUF_READY;
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}
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@ -395,14 +381,14 @@ static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request *
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spin_lock_irqsave(&host->lock, flags);
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host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m |
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IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
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IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
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host->imask = IMXMCI_INT_MASK_DEFAULT;
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MMC_INT_MASK = host->imask;
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spin_unlock_irqrestore(&host->lock, flags);
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if(req && req->cmd)
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if (req && req->cmd)
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host->prev_cmd_code = req->cmd->opcode;
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host->req = NULL;
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@ -416,17 +402,17 @@ static int imxmci_finish_data(struct imxmci_host *host, unsigned int stat)
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struct mmc_data *data = host->data;
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int data_error;
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if(test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)){
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if (test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
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imx_dma_disable(host->dma);
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dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
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host->dma_dir);
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}
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if ( stat & STATUS_ERR_MASK ) {
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dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",stat);
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if(stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR))
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if (stat & STATUS_ERR_MASK) {
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dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", stat);
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if (stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR))
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data->error = -EILSEQ;
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else if(stat & STATUS_TIME_OUT_READ)
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else if (stat & STATUS_TIME_OUT_READ)
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data->error = -ETIMEDOUT;
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else
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data->error = -EIO;
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@ -445,7 +431,7 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
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{
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struct mmc_command *cmd = host->cmd;
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int i;
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u32 a,b,c;
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u32 a, b, c;
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struct mmc_data *data = host->data;
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if (!cmd)
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@ -461,18 +447,18 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
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cmd->error = -EILSEQ;
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}
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if(cmd->flags & MMC_RSP_PRESENT) {
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if(cmd->flags & MMC_RSP_136) {
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if (cmd->flags & MMC_RSP_PRESENT) {
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if (cmd->flags & MMC_RSP_136) {
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for (i = 0; i < 4; i++) {
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u32 a = MMC_RES_FIFO & 0xffff;
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u32 b = MMC_RES_FIFO & 0xffff;
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cmd->resp[i] = a<<16 | b;
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u32 d = MMC_RES_FIFO & 0xffff;
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u32 e = MMC_RES_FIFO & 0xffff;
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cmd->resp[i] = d << 16 | e;
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}
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} else {
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a = MMC_RES_FIFO & 0xffff;
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b = MMC_RES_FIFO & 0xffff;
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c = MMC_RES_FIFO & 0xffff;
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cmd->resp[0] = a<<24 | b<<8 | c>>8;
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cmd->resp[0] = a << 24 | b << 8 | c >> 8;
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}
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}
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@ -485,35 +471,33 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
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/* Wait for FIFO to be empty before starting DMA write */
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stat = MMC_STATUS;
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if(imxmci_busy_wait_for_status(host, &stat,
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STATUS_APPL_BUFF_FE,
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40, "imxmci_cmd_done DMA WR") < 0) {
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if (imxmci_busy_wait_for_status(host, &stat,
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STATUS_APPL_BUFF_FE,
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40, "imxmci_cmd_done DMA WR") < 0) {
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cmd->error = -EIO;
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imxmci_finish_data(host, stat);
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if(host->req)
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if (host->req)
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imxmci_finish_request(host, host->req);
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dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n",
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stat);
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stat);
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return 0;
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}
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if(test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
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if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
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imx_dma_enable(host->dma);
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}
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}
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} else {
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struct mmc_request *req;
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imxmci_stop_clock(host);
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req = host->req;
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if(data)
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if (data)
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imxmci_finish_data(host, stat);
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if( req ) {
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if (req)
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imxmci_finish_request(host, req);
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} else {
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else
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dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n");
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}
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}
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return 1;
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@ -535,11 +519,10 @@ static int imxmci_data_done(struct imxmci_host *host, unsigned int stat)
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} else {
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struct mmc_request *req;
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req = host->req;
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if( req ) {
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if (req)
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imxmci_finish_request(host, req);
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} else {
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else
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dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n");
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}
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}
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return 1;
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@ -552,7 +535,7 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
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int trans_done = 0;
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unsigned int stat = *pstat;
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if(host->actual_bus_width != MMC_BUS_WIDTH_4)
|
||||
if (host->actual_bus_width != MMC_BUS_WIDTH_4)
|
||||
burst_len = 16;
|
||||
else
|
||||
burst_len = 64;
|
||||
|
|
@ -563,27 +546,27 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
|
|||
|
||||
udelay(20); /* required for clocks < 8MHz*/
|
||||
|
||||
if(host->dma_dir == DMA_FROM_DEVICE) {
|
||||
if (host->dma_dir == DMA_FROM_DEVICE) {
|
||||
imxmci_busy_wait_for_status(host, &stat,
|
||||
STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE |
|
||||
STATUS_TIME_OUT_READ,
|
||||
50, "imxmci_cpu_driven_data read");
|
||||
STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE |
|
||||
STATUS_TIME_OUT_READ,
|
||||
50, "imxmci_cpu_driven_data read");
|
||||
|
||||
while((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) &&
|
||||
!(stat & STATUS_TIME_OUT_READ) &&
|
||||
(host->data_cnt < 512)) {
|
||||
while ((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) &&
|
||||
!(stat & STATUS_TIME_OUT_READ) &&
|
||||
(host->data_cnt < 512)) {
|
||||
|
||||
udelay(20); /* required for clocks < 8MHz*/
|
||||
|
||||
for(i = burst_len; i>=2 ; i-=2) {
|
||||
for (i = burst_len; i >= 2 ; i -= 2) {
|
||||
u16 data;
|
||||
data = MMC_BUFFER_ACCESS;
|
||||
udelay(10); /* required for clocks < 8MHz*/
|
||||
if(host->data_cnt+2 <= host->dma_size) {
|
||||
if (host->data_cnt+2 <= host->dma_size) {
|
||||
*(host->data_ptr++) = data;
|
||||
} else {
|
||||
if(host->data_cnt < host->dma_size)
|
||||
*(u8*)(host->data_ptr) = data;
|
||||
if (host->data_cnt < host->dma_size)
|
||||
*(u8 *)(host->data_ptr) = data;
|
||||
}
|
||||
host->data_cnt += 2;
|
||||
}
|
||||
|
|
@ -594,13 +577,13 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
|
|||
host->data_cnt, burst_len, stat);
|
||||
}
|
||||
|
||||
if((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512))
|
||||
if ((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512))
|
||||
trans_done = 1;
|
||||
|
||||
if(host->dma_size & 0x1ff)
|
||||
if (host->dma_size & 0x1ff)
|
||||
stat &= ~STATUS_CRC_READ_ERR;
|
||||
|
||||
if(stat & STATUS_TIME_OUT_READ) {
|
||||
if (stat & STATUS_TIME_OUT_READ) {
|
||||
dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n",
|
||||
stat);
|
||||
trans_done = -1;
|
||||
|
|
@ -608,12 +591,12 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
|
|||
|
||||
} else {
|
||||
imxmci_busy_wait_for_status(host, &stat,
|
||||
STATUS_APPL_BUFF_FE,
|
||||
20, "imxmci_cpu_driven_data write");
|
||||
STATUS_APPL_BUFF_FE,
|
||||
20, "imxmci_cpu_driven_data write");
|
||||
|
||||
while((stat & STATUS_APPL_BUFF_FE) &&
|
||||
(host->data_cnt < host->dma_size)) {
|
||||
if(burst_len >= host->dma_size - host->data_cnt) {
|
||||
while ((stat & STATUS_APPL_BUFF_FE) &&
|
||||
(host->data_cnt < host->dma_size)) {
|
||||
if (burst_len >= host->dma_size - host->data_cnt) {
|
||||
burst_len = host->dma_size - host->data_cnt;
|
||||
host->data_cnt = host->dma_size;
|
||||
trans_done = 1;
|
||||
|
|
@ -621,7 +604,7 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
|
|||
host->data_cnt += burst_len;
|
||||
}
|
||||
|
||||
for(i = burst_len; i>0 ; i-=2)
|
||||
for (i = burst_len; i > 0 ; i -= 2)
|
||||
MMC_BUFFER_ACCESS = *(host->data_ptr++);
|
||||
|
||||
stat = MMC_STATUS;
|
||||
|
|
@ -671,7 +654,7 @@ static void imxmci_tasklet_fnc(unsigned long data)
|
|||
unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */
|
||||
int timeout = 0;
|
||||
|
||||
if(atomic_read(&host->stuck_timeout) > 4) {
|
||||
if (atomic_read(&host->stuck_timeout) > 4) {
|
||||
char *what;
|
||||
timeout = 1;
|
||||
stat = MMC_STATUS;
|
||||
|
|
@ -683,7 +666,7 @@ static void imxmci_tasklet_fnc(unsigned long data)
|
|||
what = "RESP";
|
||||
else
|
||||
if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
|
||||
if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events))
|
||||
if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events))
|
||||
what = "DATA";
|
||||
else
|
||||
what = "DMA";
|
||||
|
|
@ -691,18 +674,18 @@ static void imxmci_tasklet_fnc(unsigned long data)
|
|||
what = "???";
|
||||
|
||||
dev_err(mmc_dev(host->mmc), "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
|
||||
what, stat, MMC_INT_MASK);
|
||||
what, stat, MMC_INT_MASK);
|
||||
dev_err(mmc_dev(host->mmc), "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
|
||||
MMC_CMD_DAT_CONT, MMC_BLK_LEN, MMC_NOB, CCR(host->dma));
|
||||
MMC_CMD_DAT_CONT, MMC_BLK_LEN, MMC_NOB, CCR(host->dma));
|
||||
dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n",
|
||||
host->cmd?host->cmd->opcode:0, host->prev_cmd_code, 1<<host->actual_bus_width, host->dma_size);
|
||||
host->cmd?host->cmd->opcode:0, host->prev_cmd_code, 1 << host->actual_bus_width, host->dma_size);
|
||||
}
|
||||
|
||||
if(!host->present || timeout)
|
||||
if (!host->present || timeout)
|
||||
host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ |
|
||||
STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR;
|
||||
STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR;
|
||||
|
||||
if(test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
|
||||
if (test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
|
||||
clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
|
||||
|
||||
stat = MMC_STATUS;
|
||||
|
|
@ -713,63 +696,62 @@ static void imxmci_tasklet_fnc(unsigned long data)
|
|||
*/
|
||||
stat |= host->status_reg;
|
||||
|
||||
if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
|
||||
if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
|
||||
stat &= ~STATUS_CRC_READ_ERR;
|
||||
|
||||
if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
|
||||
if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
|
||||
imxmci_busy_wait_for_status(host, &stat,
|
||||
STATUS_END_CMD_RESP | STATUS_ERR_MASK,
|
||||
20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
|
||||
STATUS_END_CMD_RESP | STATUS_ERR_MASK,
|
||||
20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
|
||||
}
|
||||
|
||||
if(stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) {
|
||||
if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
|
||||
if (stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) {
|
||||
if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
|
||||
imxmci_cmd_done(host, stat);
|
||||
if(host->data && (stat & STATUS_ERR_MASK))
|
||||
if (host->data && (stat & STATUS_ERR_MASK))
|
||||
imxmci_data_done(host, stat);
|
||||
}
|
||||
|
||||
if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
|
||||
if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
|
||||
stat |= MMC_STATUS;
|
||||
if(imxmci_cpu_driven_data(host, &stat)){
|
||||
if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
|
||||
if (imxmci_cpu_driven_data(host, &stat)) {
|
||||
if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
|
||||
imxmci_cmd_done(host, stat);
|
||||
atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m,
|
||||
&host->pending_events);
|
||||
&host->pending_events);
|
||||
imxmci_data_done(host, stat);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
|
||||
!test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
|
||||
if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
|
||||
!test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
|
||||
|
||||
stat = MMC_STATUS;
|
||||
/* Same as above */
|
||||
stat |= host->status_reg;
|
||||
|
||||
if(host->dma_dir == DMA_TO_DEVICE) {
|
||||
if (host->dma_dir == DMA_TO_DEVICE)
|
||||
data_dir_mask = STATUS_WRITE_OP_DONE;
|
||||
} else {
|
||||
else
|
||||
data_dir_mask = STATUS_DATA_TRANS_DONE;
|
||||
}
|
||||
|
||||
if(stat & data_dir_mask) {
|
||||
if (stat & data_dir_mask) {
|
||||
clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
|
||||
imxmci_data_done(host, stat);
|
||||
}
|
||||
}
|
||||
|
||||
if(test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) {
|
||||
if (test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) {
|
||||
|
||||
if(host->cmd)
|
||||
if (host->cmd)
|
||||
imxmci_cmd_done(host, STATUS_TIME_OUT_RESP);
|
||||
|
||||
if(host->data)
|
||||
if (host->data)
|
||||
imxmci_data_done(host, STATUS_TIME_OUT_READ |
|
||||
STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR);
|
||||
|
||||
if(host->req)
|
||||
if (host->req)
|
||||
imxmci_finish_request(host, host->req);
|
||||
|
||||
mmc_detect_change(host->mmc, msecs_to_jiffies(100));
|
||||
|
|
@ -796,9 +778,8 @@ static void imxmci_request(struct mmc_host *mmc, struct mmc_request *req)
|
|||
if (req->data->flags & MMC_DATA_WRITE)
|
||||
cmdat |= CMD_DAT_CONT_WRITE;
|
||||
|
||||
if (req->data->flags & MMC_DATA_STREAM) {
|
||||
if (req->data->flags & MMC_DATA_STREAM)
|
||||
cmdat |= CMD_DAT_CONT_STREAM_BLOCK;
|
||||
}
|
||||
}
|
||||
|
||||
imxmci_start_cmd(host, req->cmd, cmdat);
|
||||
|
|
@ -811,36 +792,36 @@ static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|||
struct imxmci_host *host = mmc_priv(mmc);
|
||||
int prescaler;
|
||||
|
||||
if( ios->bus_width==MMC_BUS_WIDTH_4 ) {
|
||||
if (ios->bus_width == MMC_BUS_WIDTH_4) {
|
||||
host->actual_bus_width = MMC_BUS_WIDTH_4;
|
||||
imx_gpio_mode(PB11_PF_SD_DAT3);
|
||||
}else{
|
||||
} else {
|
||||
host->actual_bus_width = MMC_BUS_WIDTH_1;
|
||||
imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
|
||||
}
|
||||
|
||||
if ( host->power_mode != ios->power_mode ) {
|
||||
if (host->power_mode != ios->power_mode) {
|
||||
switch (ios->power_mode) {
|
||||
case MMC_POWER_OFF:
|
||||
break;
|
||||
break;
|
||||
case MMC_POWER_UP:
|
||||
set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
|
||||
break;
|
||||
break;
|
||||
case MMC_POWER_ON:
|
||||
break;
|
||||
break;
|
||||
}
|
||||
host->power_mode = ios->power_mode;
|
||||
}
|
||||
|
||||
if ( ios->clock ) {
|
||||
if (ios->clock) {
|
||||
unsigned int clk;
|
||||
|
||||
/* The prescaler is 5 for PERCLK2 equal to 96MHz
|
||||
* then 96MHz / 5 = 19.2 MHz
|
||||
*/
|
||||
clk = clk_get_rate(host->clk);
|
||||
prescaler=(clk+(CLK_RATE*7)/8)/CLK_RATE;
|
||||
switch(prescaler) {
|
||||
prescaler = (clk + (CLK_RATE * 7) / 8) / CLK_RATE;
|
||||
switch (prescaler) {
|
||||
case 0:
|
||||
case 1: prescaler = 0;
|
||||
break;
|
||||
|
|
@ -858,22 +839,22 @@ static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|||
dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n",
|
||||
clk, prescaler);
|
||||
|
||||
for(clk=0; clk<8; clk++) {
|
||||
for (clk = 0; clk < 8; clk++) {
|
||||
int x;
|
||||
x = CLK_RATE / (1<<clk);
|
||||
if( x <= ios->clock)
|
||||
x = CLK_RATE / (1 << clk);
|
||||
if (x <= ios->clock)
|
||||
break;
|
||||
}
|
||||
|
||||
MMC_STR_STP_CLK |= STR_STP_CLK_ENABLE; /* enable controller */
|
||||
|
||||
imxmci_stop_clock(host);
|
||||
MMC_CLK_RATE = (prescaler<<3) | clk;
|
||||
MMC_CLK_RATE = (prescaler << 3) | clk;
|
||||
/*
|
||||
* Under my understanding, clock should not be started there, because it would
|
||||
* initiate SDHC sequencer and send last or random command into card
|
||||
*/
|
||||
/*imxmci_start_clock(host);*/
|
||||
/* imxmci_start_clock(host); */
|
||||
|
||||
dev_dbg(mmc_dev(host->mmc), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE);
|
||||
} else {
|
||||
|
|
@ -915,10 +896,10 @@ static void imxmci_check_status(unsigned long data)
|
|||
tasklet_schedule(&host->tasklet);
|
||||
}
|
||||
|
||||
if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) ||
|
||||
test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
|
||||
if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) ||
|
||||
test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
|
||||
atomic_inc(&host->stuck_timeout);
|
||||
if(atomic_read(&host->stuck_timeout) > 4)
|
||||
if (atomic_read(&host->stuck_timeout) > 4)
|
||||
tasklet_schedule(&host->tasklet);
|
||||
} else {
|
||||
atomic_set(&host->stuck_timeout, 0);
|
||||
|
|
@ -995,9 +976,9 @@ static int imxmci_probe(struct platform_device *pdev)
|
|||
|
||||
imxmci_softreset();
|
||||
|
||||
if ( MMC_REV_NO != 0x390 ) {
|
||||
if (MMC_REV_NO != 0x390) {
|
||||
dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
|
||||
MMC_REV_NO);
|
||||
MMC_REV_NO);
|
||||
goto out;
|
||||
}
|
||||
|
||||
|
|
@ -1012,7 +993,7 @@ static int imxmci_probe(struct platform_device *pdev)
|
|||
ret = -EBUSY;
|
||||
goto out;
|
||||
}
|
||||
host->dma_allocated=1;
|
||||
host->dma_allocated = 1;
|
||||
imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host);
|
||||
|
||||
tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host);
|
||||
|
|
@ -1032,7 +1013,7 @@ static int imxmci_probe(struct platform_device *pdev)
|
|||
host->timer.data = (unsigned long)host;
|
||||
host->timer.function = imxmci_check_status;
|
||||
add_timer(&host->timer);
|
||||
mod_timer(&host->timer, jiffies + (HZ>>1));
|
||||
mod_timer(&host->timer, jiffies + (HZ >> 1));
|
||||
|
||||
platform_set_drvdata(pdev, mmc);
|
||||
|
||||
|
|
@ -1042,9 +1023,9 @@ static int imxmci_probe(struct platform_device *pdev)
|
|||
|
||||
out:
|
||||
if (host) {
|
||||
if(host->dma_allocated){
|
||||
if (host->dma_allocated) {
|
||||
imx_dma_free(host->dma);
|
||||
host->dma_allocated=0;
|
||||
host->dma_allocated = 0;
|
||||
}
|
||||
if (host->clk) {
|
||||
clk_disable(host->clk);
|
||||
|
|
@ -1072,9 +1053,9 @@ static int imxmci_remove(struct platform_device *pdev)
|
|||
mmc_remove_host(mmc);
|
||||
|
||||
free_irq(host->irq, host);
|
||||
if(host->dma_allocated){
|
||||
if (host->dma_allocated) {
|
||||
imx_dma_free(host->dma);
|
||||
host->dma_allocated=0;
|
||||
host->dma_allocated = 0;
|
||||
}
|
||||
|
||||
tasklet_kill(&host->tasklet);
|
||||
|
|
@ -1109,7 +1090,7 @@ static int imxmci_resume(struct platform_device *dev)
|
|||
|
||||
if (mmc) {
|
||||
host = mmc_priv(mmc);
|
||||
if(host)
|
||||
if (host)
|
||||
set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
|
||||
ret = mmc_resume_host(mmc);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue