MIPS: math-emu: Emulate MIPSr6 sel.fmt instruction
Add support for emulating the MIPSr6 sel.fmt instruction, which was previously missing from the FPU emulation code. This instruction selects its result from 2 possible source registers, based upon bit 0 of the destination register, and is valid only for S (single) & D (double) data types. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13153/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -1675,7 +1675,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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union ieee754sp(*b) (union ieee754sp, union ieee754sp);
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union ieee754sp(*u) (union ieee754sp);
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} handler;
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union ieee754sp fs, ft;
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union ieee754sp fd, fs, ft;
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switch (MIPSInst_FUNC(ir)) {
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/* binary ops */
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@ -1946,6 +1946,17 @@ copcsr:
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rfmt = w_fmt;
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goto copcsr;
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case fsel_op:
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if (!cpu_has_mips_r6)
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return SIGILL;
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SPFROMREG(fd, MIPSInst_FD(ir));
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if (fd.bits & 0x1)
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SPFROMREG(rv.s, MIPSInst_FT(ir));
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else
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SPFROMREG(rv.s, MIPSInst_FS(ir));
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break;
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case fcvtl_op:
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if (!cpu_has_mips_3_4_5_64_r2_r6)
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return SIGILL;
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@ -1994,7 +2005,7 @@ copcsr:
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}
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case d_fmt: {
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union ieee754dp fs, ft;
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union ieee754dp fd, fs, ft;
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union {
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union ieee754dp(*b) (union ieee754dp, union ieee754dp);
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union ieee754dp(*u) (union ieee754dp);
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@ -2244,6 +2255,17 @@ dcopuop:
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rfmt = w_fmt;
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goto copcsr;
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case fsel_op:
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if (!cpu_has_mips_r6)
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return SIGILL;
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DPFROMREG(fd, MIPSInst_FD(ir));
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if (fd.bits & 0x1)
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DPFROMREG(rv.d, MIPSInst_FT(ir));
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else
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DPFROMREG(rv.d, MIPSInst_FS(ir));
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break;
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case fcvtl_op:
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if (!cpu_has_mips_3_4_5_64_r2_r6)
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return SIGILL;
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