redonkable
/
alistair23-linux
1
0
Fork 0
Code Releases Activity

ARM: MM: Add DT binding for Feroceon L2 cache 

Instantiate the L2 cache from DT. Indicate in DT where the cache
control register is so that it is possible to enable/disable write
through on the CPU.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
hifive-unleashed-5.1
Andrew Lunn 2014-02-22 20:14:52 +01:00 committed by Jason Cooper
parent 3c317d00ba
commit 4b8f7a11c9
4 changed files with 64 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
Documentation/devicetree/bindings/arm/mrvl/feroceon.txt 100644
View File

@ -0,0 +1,16 @@
* Marvell Feroceon Cache
Required properties:
- compatible : Should be either "marvell,feroceon-cache" or
"marvell,kirkwood-cache".
Optional properties:
- reg : Address of the L2 cache control register. Mandatory for
"marvell,kirkwood-cache", not used by "marvell,feroceon-cache"
Example:
l2: l2-cache@20128 {
compatible = "marvell,kirkwood-cache";
reg = <0x20128 0x4>;
};

2
arch/arm/include/asm/hardware/cache-feroceon-l2.h
View File

@ -9,3 +9,5 @@
*/
extern void __init feroceon_l2_init(int l2_wt_override);
extern int __init feroceon_of_init(void);

18
arch/arm/mach-kirkwood/board-dt.c
View File

@ -42,19 +42,6 @@ static void __init kirkwood_map_io(void)
iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
}
static void __init kirkwood_l2_init(void)
{
#ifdef CONFIG_CACHE_FEROCEON_L2
#ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
feroceon_l2_init(1);
#else
writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
feroceon_l2_init(0);
#endif
#endif
}
static struct resource kirkwood_cpufreq_resources[] = {
[0] = {
.start = CPU_CONTROL_PHYS,
@ -211,8 +198,9 @@ static void __init kirkwood_dt_init(void)
BUG_ON(mvebu_mbus_dt_init());
kirkwood_l2_init();
#ifdef CONFIG_CACHE_FEROCEON_L2
feroceon_of_init();
#endif
kirkwood_cpufreq_init();
kirkwood_cpuidle_init();

43
arch/arm/mm/cache-feroceon-l2.c
View File

@ -13,11 +13,16 @@
*/
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/highmem.h>
#include <linux/io.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/hardware/cache-feroceon-l2.h>
#define L2_WRITETHROUGH_KIRKWOOD BIT(4)
/*
* Low-level cache maintenance operations.
*
@ -350,3 +355,41 @@ void __init feroceon_l2_init(int __l2_wt_override)
printk(KERN_INFO "Feroceon L2: Cache support initialised%s.\n",
l2_wt_override ? ", in WT override mode" : "");
}
#ifdef CONFIG_OF
static const struct of_device_id feroceon_ids[] __initconst = {
{ .compatible = "marvell,kirkwood-cache"},
{ .compatible = "marvell,feroceon-cache"},
{}
};
int __init feroceon_of_init(void)
{
struct device_node *node;
void __iomem *base;
bool l2_wt_override = false;
struct resource res;
#if defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
l2_wt_override = true;
#endif
node = of_find_matching_node(NULL, feroceon_ids);
if (node && of_device_is_compatible(node, "marvell,kirkwood-cache")) {
if (of_address_to_resource(node, 0, &res))
return -ENODEV;
base = ioremap(res.start, resource_size(&res));
if (!base)
return -ENOMEM;
if (l2_wt_override)
writel(readl(base) | L2_WRITETHROUGH_KIRKWOOD, base);
else
writel(readl(base) & ~L2_WRITETHROUGH_KIRKWOOD, base);
}
feroceon_l2_init(l2_wt_override);
return 0;
}
#endif