enic: workaround A0 erratum
A0 revision ASIC has an erratum on the RQ desc cache on chip where the cache can become corrupted causing pkt buf writes to wrong locations. The s/w workaround is to post a dummy RQ desc in the ring every 32 descs, causing a flush of the cache. A0 parts are not production, but there are enough of these parts in the wild in test setups to warrant including workaround. A1 revision ASIC parts fix erratum. Signed-off-by: Scott Feldman <scofeldm@cisco.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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27e6c7d338
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@ -851,6 +851,50 @@ static int enic_rq_alloc_buf(struct vnic_rq *rq)
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return 0;
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}
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static int enic_rq_alloc_buf_a1(struct vnic_rq *rq)
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{
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struct rq_enet_desc *desc = vnic_rq_next_desc(rq);
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if (vnic_rq_posting_soon(rq)) {
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/* SW workaround for A0 HW erratum: if we're just about
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* to write posted_index, insert a dummy desc
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* of type resvd
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*/
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rq_enet_desc_enc(desc, 0, RQ_ENET_TYPE_RESV2, 0);
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vnic_rq_post(rq, 0, 0, 0, 0);
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} else {
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return enic_rq_alloc_buf(rq);
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}
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return 0;
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}
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static int enic_set_rq_alloc_buf(struct enic *enic)
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{
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enum vnic_dev_hw_version hw_ver;
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int err;
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err = vnic_dev_hw_version(enic->vdev, &hw_ver);
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if (err)
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return err;
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switch (hw_ver) {
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case VNIC_DEV_HW_VER_A1:
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enic->rq_alloc_buf = enic_rq_alloc_buf_a1;
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break;
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case VNIC_DEV_HW_VER_A2:
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case VNIC_DEV_HW_VER_UNKNOWN:
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enic->rq_alloc_buf = enic_rq_alloc_buf;
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break;
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default:
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return -ENODEV;
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}
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return 0;
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}
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static int enic_get_skb_header(struct sk_buff *skb, void **iphdr,
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void **tcph, u64 *hdr_flags, void *priv)
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{
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@ -1058,7 +1102,7 @@ static int enic_poll(struct napi_struct *napi, int budget)
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/* Replenish RQ
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*/
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vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf);
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vnic_rq_fill(&enic->rq[0], enic->rq_alloc_buf);
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} else {
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@ -1093,7 +1137,7 @@ static int enic_poll_msix(struct napi_struct *napi, int budget)
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/* Replenish RQ
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*/
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vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf);
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vnic_rq_fill(&enic->rq[0], enic->rq_alloc_buf);
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/* Return intr event credits for this polling
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* cycle. An intr event is the completion of a
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@ -1269,7 +1313,7 @@ static int enic_open(struct net_device *netdev)
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}
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for (i = 0; i < enic->rq_count; i++) {
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err = vnic_rq_fill(&enic->rq[i], enic_rq_alloc_buf);
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err = vnic_rq_fill(&enic->rq[i], enic->rq_alloc_buf);
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if (err) {
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printk(KERN_ERR PFX
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"%s: Unable to alloc receive buffers.\n",
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@ -349,6 +349,25 @@ int vnic_dev_fw_info(struct vnic_dev *vdev,
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return err;
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}
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int vnic_dev_hw_version(struct vnic_dev *vdev, enum vnic_dev_hw_version *hw_ver)
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{
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struct vnic_devcmd_fw_info *fw_info;
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int err;
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err = vnic_dev_fw_info(vdev, &fw_info);
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if (err)
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return err;
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if (strncmp(fw_info->hw_version, "A1", sizeof("A1")) == 0)
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*hw_ver = VNIC_DEV_HW_VER_A1;
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else if (strncmp(fw_info->hw_version, "A2", sizeof("A2")) == 0)
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*hw_ver = VNIC_DEV_HW_VER_A2;
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else
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*hw_ver = VNIC_DEV_HW_VER_UNKNOWN;
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return 0;
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}
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int vnic_dev_spec(struct vnic_dev *vdev, unsigned int offset, unsigned int size,
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void *value)
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{
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@ -41,6 +41,12 @@ static inline void writeq(u64 val, void __iomem *reg)
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}
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#endif
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enum vnic_dev_hw_version {
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VNIC_DEV_HW_VER_UNKNOWN,
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VNIC_DEV_HW_VER_A1,
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VNIC_DEV_HW_VER_A2,
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};
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enum vnic_dev_intr_mode {
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VNIC_DEV_INTR_MODE_UNKNOWN,
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VNIC_DEV_INTR_MODE_INTX,
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@ -88,6 +94,8 @@ int vnic_dev_cmd(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
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u64 *a0, u64 *a1, int wait);
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int vnic_dev_fw_info(struct vnic_dev *vdev,
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struct vnic_devcmd_fw_info **fw_info);
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int vnic_dev_hw_version(struct vnic_dev *vdev,
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enum vnic_dev_hw_version *hw_ver);
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int vnic_dev_spec(struct vnic_dev *vdev, unsigned int offset, unsigned int size,
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void *value);
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int vnic_dev_stats_clear(struct vnic_dev *vdev);
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@ -143,6 +143,11 @@ static inline void vnic_rq_post(struct vnic_rq *rq,
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}
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}
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static inline int vnic_rq_posting_soon(struct vnic_rq *rq)
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{
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return ((rq->to_use->index & VNIC_RQ_RETURN_RATE) == 0);
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}
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static inline void vnic_rq_return_descs(struct vnic_rq *rq, unsigned int count)
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{
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rq->ring.desc_avail += count;
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@ -186,7 +191,7 @@ static inline int vnic_rq_fill(struct vnic_rq *rq,
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{
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int err;
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while (vnic_rq_desc_avail(rq) > 1) {
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while (vnic_rq_desc_avail(rq) > 0) {
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err = (*buf_fill)(rq);
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if (err)
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