ARM: OMAP: Add GPMC support for OMAP2
Implement basic support for General-Purpose Memory Controller as found on OMAP2420. Dynamic CS address space allocation still needs to be done. Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com>hifive-unleashed-5.1
Juha Yrjola
Tony Lindgren
parent
7ff879dbcd
commit
4bbbc1adc2
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@ -3,7 +3,8 @@
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#
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# Common support
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obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o serial.o
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obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o \
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serial.o gpmc.o
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obj-$(CONFIG_OMAP_MPU_TIMER) += timer-gp.o
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@ -0,0 +1,209 @@
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/*
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* GPMC support functions
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*
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* Copyright (C) 2005-2006 Nokia Corporation
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*
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* Author: Juha Yrjola
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <asm/io.h>
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#include <asm/arch/gpmc.h>
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#undef DEBUG
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#define GPMC_BASE 0x6800a000
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#define GPMC_REVISION 0x00
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#define GPMC_SYSCONFIG 0x10
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#define GPMC_SYSSTATUS 0x14
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#define GPMC_IRQSTATUS 0x18
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#define GPMC_IRQENABLE 0x1c
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#define GPMC_TIMEOUT_CONTROL 0x40
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#define GPMC_ERR_ADDRESS 0x44
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#define GPMC_ERR_TYPE 0x48
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#define GPMC_CONFIG 0x50
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#define GPMC_STATUS 0x54
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#define GPMC_PREFETCH_CONFIG1 0x1e0
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#define GPMC_PREFETCH_CONFIG2 0x1e4
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#define GPMC_PREFETCH_CONTROL 0x1e8
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#define GPMC_PREFETCH_STATUS 0x1f0
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#define GPMC_ECC_CONFIG 0x1f4
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#define GPMC_ECC_CONTROL 0x1f8
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#define GPMC_ECC_SIZE_CONFIG 0x1fc
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#define GPMC_CS0 0x60
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#define GPMC_CS_SIZE 0x30
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static void __iomem *gpmc_base =
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(void __iomem *) IO_ADDRESS(GPMC_BASE);
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static void __iomem *gpmc_cs_base =
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(void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
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static struct clk *gpmc_l3_clk;
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static void gpmc_write_reg(int idx, u32 val)
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{
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__raw_writel(val, gpmc_base + idx);
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}
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static u32 gpmc_read_reg(int idx)
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{
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return __raw_readl(gpmc_base + idx);
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}
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void gpmc_cs_write_reg(int cs, int idx, u32 val)
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{
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void __iomem *reg_addr;
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reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx;
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__raw_writel(val, reg_addr);
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}
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u32 gpmc_cs_read_reg(int cs, int idx)
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{
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return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
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}
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/* TODO: Add support for gpmc_fck to clock framework and use it */
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static unsigned long gpmc_get_fclk_period(void)
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{
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/* In picoseconds */
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return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000);
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}
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unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
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{
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unsigned long tick_ps;
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/* Calculate in picosecs to yield more exact results */
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tick_ps = gpmc_get_fclk_period();
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return (time_ns * 1000 + tick_ps - 1) / tick_ps;
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}
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#ifdef DEBUG
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static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
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int time, int div, const char *name)
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#else
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static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
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int time)
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#endif
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{
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u32 l;
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int ticks, mask, nr_bits;
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if (time == 0)
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ticks = 0;
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else
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ticks = gpmc_ns_to_ticks(time);
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nr_bits = end_bit - st_bit + 1;
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if (ticks >= 1 << nr_bits)
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return -1;
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mask = (1 << nr_bits) - 1;
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l = gpmc_cs_read_reg(cs, reg);
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#ifdef DEBUG
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printk(KERN_INFO "GPMC CS%d: %-10s: %d ticks, %3lu ns (was %i ticks)\n",
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cs, name, ticks, gpmc_get_clk_period(div) * ticks / 1000,
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(l >> st_bit) & mask);
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#endif
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l &= ~(mask << st_bit);
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l |= ticks << st_bit;
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gpmc_cs_write_reg(cs, reg, l);
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return 0;
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}
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#ifdef DEBUG
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#define GPMC_SET_ONE(reg, st, end, field) \
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if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
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t->field, #field) < 0) \
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return -1
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#else
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#define GPMC_SET_ONE(reg, st, end, field) \
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if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
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return -1
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#endif
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int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
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{
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int div;
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u32 l;
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l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
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div = l / gpmc_get_fclk_period();
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if (div > 4)
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return -1;
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if (div < 0)
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div = 1;
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return div;
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}
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int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
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{
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int div;
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u32 l;
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div = gpmc_cs_calc_divider(cs, t->sync_clk);
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if (div < 0)
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return -1;
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GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
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GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
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GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
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GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
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GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
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GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
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GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
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GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
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GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
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GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
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GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
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GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
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GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
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GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
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#ifdef DEBUG
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printk(KERN_INFO "GPMC CLK period is %d (div %d)\n",
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cs, get_gpmc_clk_period(div), div);
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#endif
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l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
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l &= ~0x03;
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l |= (div - 1);
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return 0;
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}
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unsigned long gpmc_cs_get_base_addr(int cs)
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{
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return (gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7) & 0x1f) << 24;
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}
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void __init gpmc_init(void)
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{
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u32 l;
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gpmc_l3_clk = clk_get(NULL, "core_l3_ck");
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BUG_ON(IS_ERR(gpmc_l3_clk));
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l = gpmc_read_reg(GPMC_REVISION);
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printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
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/* Set smart idle mode and automatic L3 clock gating */
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l = gpmc_read_reg(GPMC_SYSCONFIG);
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l &= 0x03 << 3;
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l |= (0x02 << 3) | (1 << 0);
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gpmc_write_reg(GPMC_SYSCONFIG, l);
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}
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@ -27,6 +27,7 @@
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extern void omap_sram_init(void);
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extern int omap2_clk_init(void);
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extern void omap2_check_revision(void);
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extern void gpmc_init(void);
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/*
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* The machine specific code may provide the extra mapping besides the
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@ -67,4 +68,5 @@ void __init omap2_init_common_hw(void)
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{
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omap2_mux_init();
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omap2_clk_init();
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gpmc_init();
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}
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@ -0,0 +1,91 @@
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/*
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* General-Purpose Memory Controller for OMAP2
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*
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* Copyright (C) 2005-2006 Nokia Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __OMAP2_GPMC_H
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#define __OMAP2_GPMC_H
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#define GPMC_CS_CONFIG1 0x00
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#define GPMC_CS_CONFIG2 0x04
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#define GPMC_CS_CONFIG3 0x08
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#define GPMC_CS_CONFIG4 0x0c
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#define GPMC_CS_CONFIG5 0x10
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#define GPMC_CS_CONFIG6 0x14
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#define GPMC_CS_CONFIG7 0x18
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#define GPMC_CS_NAND_COMMAND 0x1c
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#define GPMC_CS_NAND_ADDRESS 0x20
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#define GPMC_CS_NAND_DATA 0x24
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#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
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#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 20)
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#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
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#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
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#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
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#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
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#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
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#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
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#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
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#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
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#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
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#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
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#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
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#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
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#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
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#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
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#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(1)
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#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
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#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
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#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
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#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
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#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
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#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
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/*
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* Note that all values in this struct are in nanoseconds, while
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* the register values are in gpmc_fck cycles.
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*/
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struct gpmc_timings {
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/* Minimum clock period for synchronous mode */
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u16 sync_clk;
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/* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
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u16 cs_on; /* Assertion time */
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u16 cs_rd_off; /* Read deassertion time */
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u16 cs_wr_off; /* Write deassertion time */
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/* ADV signal timings corresponding to GPMC_CONFIG3 */
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u16 adv_on; /* Assertion time */
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u16 adv_rd_off; /* Read deassertion time */
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u16 adv_wr_off; /* Write deassertion time */
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/* WE signals timings corresponding to GPMC_CONFIG4 */
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u16 we_on; /* WE assertion time */
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u16 we_off; /* WE deassertion time */
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/* OE signals timings corresponding to GPMC_CONFIG4 */
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u16 oe_on; /* OE assertion time */
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u16 oe_off; /* OE deassertion time */
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/* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
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u16 page_burst_access; /* Multiple access word delay */
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u16 access; /* Start-cycle to first data valid delay */
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u16 rd_cycle; /* Total read cycle time */
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u16 wr_cycle; /* Total write cycle time */
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};
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extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
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extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
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extern u32 gpmc_cs_read_reg(int cs, int idx);
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extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
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extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
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extern unsigned long gpmc_cs_get_base_addr(int cs);
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#endif
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