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Blackfin arch: update ANOMALY handling 

update lists for 533, 537, and add SSYNC workaround into assembly files.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
hifive-unleashed-5.1
Robin Getz 2007-06-21 11:34:16 +08:00 committed by Bryan Wu
parent 0864a4e201
commit 4bf3f3cbb6
9 changed files with 197 additions and 25 deletions
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5
arch/blackfin/lib/memcmp.S
View File

@ -61,7 +61,12 @@ ENTRY(_memcmp)
LSETUP (.Lquad_loop_s, .Lquad_loop_e) LC0=P1;
.Lquad_loop_s:
#ifdef ANOMALY_05000202
R0 = [P0++];
R1 = [I0++];
#else
MNOP || R0 = [P0++] || R1 = [I0++];
#endif
CC = R0 == R1;
IF !CC JUMP .Lquad_different;
.Lquad_loop_e:

13
arch/blackfin/lib/memcpy.S
View File

@ -94,13 +94,20 @@ ENTRY(_memcpy)
.Lmore_than_seven:
/* There's at least eight bytes to copy. */
P2 += -1; /* because we unroll one iteration */
LSETUP(.Lword_loop, .Lword_loop) LC0=P2;
LSETUP(.Lword_loops, .Lword_loope) LC0=P2;
R0 = R1;
I1 = P1;
R3 = [I1++];
.Lword_loop:
#ifdef ANOMALY_05000202
.Lword_loops:
[P0++] = R3;
.Lword_loope:
R3 = [I1++];
#else
.Lword_loops:
.Lword_loope:
MNOP || [P0++] = R3 || R3 = [I1++];
#endif
[P0++] = R3;
/* Any remaining bytes to copy? */
R3 = 0x3;

17
arch/blackfin/lib/memmove.S
View File

@ -69,8 +69,17 @@ ENTRY(_memmove)
P2 = R2; /* set remainder */
R1 = [I0++];
LSETUP (.Lquad_loop, .Lquad_loop) LC0=P1;
.Lquad_loop: MNOP || [P0++] = R1 || R1 = [I0++];
LSETUP (.Lquad_loops, .Lquad_loope) LC0=P1;
#ifdef ANOMALY_05000202
.Lquad_loops:
[P0++] = R1;
.Lquad_loope:
R1 = [I0++];
#else
.Lquad_loops:
.Lquad_loope:
MNOP || [P0++] = R1 || R1 = [I0++];
#endif
[P0++] = R1;
CC = P2 == 0; /* any remaining bytes? */
@ -93,6 +102,10 @@ ENTRY(_memmove)
R1 = B[P3--] (Z);
CC = P2 == 0;
IF CC JUMP .Lno_loop;
#ifdef ANOMALY_05000245
NOP;
NOP;
#endif
LSETUP (.Lol_s, .Lol_e) LC0 = P2;
.Lol_s: B[P0--] = R1;
.Lol_e: R1 = B[P3--] (Z);

20
arch/blackfin/mach-common/cache.S
View File

@ -123,14 +123,14 @@ ENTRY(_blackfin_icache_flush_range)
R2 = R0 & R2;
P0 = R2;
P1 = R1;
CSYNC;
CSYNC(R3);
IFLUSH [P0];
1:
IFLUSH [P0++];
CC = P0 < P1 (iu);
IF CC JUMP 1b (bp);
IFLUSH [P0];
SSYNC;
SSYNC(R3);
RTS;
ENDPROC(_blackfin_icache_flush_range)
@ -148,7 +148,7 @@ ENTRY(_blackfin_icache_dcache_flush_range)
R2 = R0 & R2;
P0 = R2;
P1 = R1;
CSYNC;
CSYNC(R3);
IFLUSH [P0];
1:
FLUSH [P0];
@ -157,7 +157,7 @@ ENTRY(_blackfin_icache_dcache_flush_range)
IF CC JUMP 1b (bp);
IFLUSH [P0];
FLUSH [P0];
SSYNC;
SSYNC(R3);
RTS;
ENDPROC(_blackfin_icache_dcache_flush_range)
@ -174,7 +174,7 @@ ENTRY(_blackfin_dcache_invalidate_range)
R2 = R0 & R2;
P0 = R2;
P1 = R1;
CSYNC;
CSYNC(R3);
FLUSHINV[P0];
1:
FLUSHINV[P0++];
@ -186,7 +186,7 @@ ENTRY(_blackfin_dcache_invalidate_range)
* so do one more.
*/
FLUSHINV[P0];
SSYNC;
SSYNC(R3);
RTS;
ENDPROC(_blackfin_dcache_invalidate_range)
@ -235,7 +235,7 @@ ENTRY(_blackfin_dcache_flush_range)
R2 = R0 & R2;
P0 = R2;
P1 = R1;
CSYNC;
CSYNC(R3);
FLUSH[P0];
1:
FLUSH[P0++];
@ -247,17 +247,17 @@ ENTRY(_blackfin_dcache_flush_range)
* one more.
*/
FLUSH[P0];
SSYNC;
SSYNC(R3);
RTS;
ENDPROC(_blackfin_dcache_flush_range)
ENTRY(_blackfin_dflush_page)
P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT);
P0 = R0;
CSYNC;
CSYNC(R3);
FLUSH[P0];
LSETUP (.Lfl1, .Lfl1) LC0 = P1;
.Lfl1: FLUSH [P0++];
SSYNC;
SSYNC(R3);
RTS;
ENDPROC(_blackfin_dflush_page)

2
arch/blackfin/mach-common/interrupt.S
View File

@ -139,7 +139,7 @@ __common_int_entry:
fp = 0;
#endif
#ifdef ANOMALY_05000283
#if defined (ANOMALY_05000283) || defined (ANOMALY_05000315)
cc = r7 == r7;
p5.h = 0xffc0;
p5.l = 0x0014;

33
include/asm-blackfin/blackfin.h
View File

@ -39,7 +39,9 @@ static inline void SSYNC (void)
#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
static inline void SSYNC (void)
{
__builtin_bfin_ssync();
__asm__ __volatile__ ("nop; nop; nop;\n\t"
"ssync;\n\t"
::);
}
#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
static inline void SSYNC (void)
@ -71,7 +73,9 @@ static inline void CSYNC (void)
#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
static inline void CSYNC (void)
{
__builtin_bfin_csync();
__asm__ __volatile__ ("nop; nop; nop;\n\t"
"ssync;\n\t"
::);
}
#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
static inline void CSYNC (void)
@ -80,6 +84,31 @@ static inline void CSYNC (void)
}
#endif
#else /* __ASSEMBLY__ */
/* SSYNC & CSYNC implementations for assembly files */
#define ssync(x) SSYNC(x)
#define csync(x) CSYNC(x)
#if defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
#elif defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
#define SSYNC(scratch) nop; nop; nop; SSYNC;
#define CSYNC(scratch) nop; nop; nop; CSYNC;
#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
#define SSYNC(scratch) SSYNC;
#define CSYNC(scratch) CSYNC;
#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */
#endif /* __ASSEMBLY__ */
#endif /* _BLACKFIN_H_ */

84
include/asm-blackfin/mach-bf533/anomaly.h
View File

@ -43,7 +43,8 @@
#endif
/* Issues that are common to 0.5, 0.4, and 0.3 silicon */
#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) \
|| defined(CONFIG_BF_REV_0_3))
#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
slot1 and store of a P register in slot 2 is not
supported */
@ -76,11 +77,16 @@
control */
#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
killed in a particular stage*/
#define ANOMALY_05000311 /* Erroneous flag pin operations under specific
sequences */
#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
registers are interrupted */
#define ANOMALY_05000311 /* Erroneous flag pin operations under specific sequences*/
#endif
#define ANOMALY_05000313 /* PPI Is Level-Sensitive on First Transfer */
#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously On
* Next System MMR Access */
#define ANOMALY_05000319 /* Internal Voltage Regulator Values of 1.05V, 1.10V
* and 1.15V Not Allowed for LQFP Packages */
#endif /* Issues that are common to 0.5, 0.4, and 0.3 silicon */
/* These issues only occur on 0.3 or 0.4 BF533 */
#if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
@ -134,14 +140,14 @@
internal voltage regulator (VDDint) to increase. */
#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
internal voltage regulator (VDDint) to decrease */
#endif
#endif /* issues only occur on 0.3 or 0.4 BF533 */
/* These issues are only on 0.4 silicon */
#if (defined(CONFIG_BF_REV_0_4))
#define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */
#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
(TDM) */
#endif
#endif /* issues are only on 0.4 silicon */
/* These issues are only on 0.3 silicon */
#if defined(CONFIG_BF_REV_0_3)
@ -170,6 +176,72 @@
#define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame
Sync Transmit Mode */
#define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */
#endif /* only on 0.3 silicon */
#if defined(CONFIG_BF_REV_0_2)
#define ANOMALY_05000067 /* Watchpoints (Hardware Breakpoints) are not
* supported */
#define ANOMALY_05000109 /* Reserved bits in SYSCFG register not set at
* power on */
#define ANOMALY_05000116 /* Trace Buffers may record discontinuities into
* emulation mode and/or exception, NMI, reset
* handlers */
#define ANOMALY_05000123 /* DTEST_COMMAND initiated memory access may be
* incorrect if data cache or DMA is active */
#define ANOMALY_05000124 /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1,
* or 1:1 */
#define ANOMALY_05000125 /* Erroneous exception when enabling cache */
#define ANOMALY_05000126 /* SPI clock polarity and phase bits incorrect
* during booting */
#define ANOMALY_05000137 /* DMEM_CONTROL is not set on Reset */
#define ANOMALY_05000138 /* SPI boot will not complete if there is a zero fill
* block in the loader file */
#define ANOMALY_05000140 /* Allowing the SPORT RX FIFO to fill will cause an
* overflow */
#define ANOMALY_05000141 /* An Infinite Stall occurs with a particular sequence
* of consecutive dual dag events */
#define ANOMALY_05000142 /* Interrupts may be lost when a programmable input
* flag is configured to be edge sensitive */
#define ANOMALY_05000143 /* A read from external memory may return a wrong
* value with data cache enabled */
#define ANOMALY_05000144 /* DMA and TESTSET conflict when both are accessing
* external memory */
#define ANOMALY_05000145 /* In PWM_OUT mode, you must enable the PPI block to
* generate a waveform from PPI_CLK */
#define ANOMALY_05000146 /* MDMA may lose the first few words of a descriptor
* chain */
#define ANOMALY_05000147 /* The source MDMA descriptor may stop with a DMA
* Error */
#define ANOMALY_05000148 /* When booting from a 16-bit asynchronous memory
* device, the upper 8-bits of each word must be
* 0x00 */
#define ANOMALY_05000153 /* Frame Delay in SPORT Multichannel Mode */
#define ANOMALY_05000154 /* SPORT TFS signal is active in Multi-channel mode
* outside of valid channels */
#define ANOMALY_05000155 /* Timer1 can not be used for PWMOUT mode when a
* certain PPI mode is in use */
#define ANOMALY_05000157 /* A killed 32-bit System MMR write will lead to
* the next system MMR access thinking it should be
* 32-bit. */
#define ANOMALY_05000163 /* SPORT transmit data is not gated by external frame
* sync in certain conditions */
#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */
#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost
* write-through cache data writes */
#define ANOMALY_05000173 /* DMA vs Core accesses to external memory */
#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */
#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */
#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an
* accumulator saturation */
#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration
* registers */
#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */
#define ANOMALY_05000191 /* PPI does not invert the Driving PPICLK edge in
* Transmit Modes */
#define ANOMALY_05000192 /* In PPI Transmit Modes with External Frame Syncs
* POLC */
#define ANOMALY_05000206 /* Internal Voltage Regulator may not start up */
#endif
#endif /* _MACH_ANOMALY_H_ */

21
include/asm-blackfin/mach-bf537/anomaly.h
View File

@ -73,8 +73,13 @@
control */
#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
killed in a particular stage*/
#define ANOMALY_05000310 /* False hardware errors caused by fetches at the
* boundary of reserved memory */
#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
registers are interrupted */
#define ANOMALY_05000313 /* PPI is level sensitive on first transfer */
#define ANOMALY_05000322 /* EMAC RMII mode at 10-Base-T speed: RX frames not
* received properly */
#endif
#if defined(CONFIG_BF_REV_0_2)
@ -114,7 +119,21 @@
DMA system instability */
#define ANOMALY_05000280 /* SPI Master boot mode does not work well with
Atmel Dataflash devices */
#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context
* is not restored */
#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
* control */
#define ANOMALY_05000283 /* System MMR Write Is Stalled Indefinitely When
* Killed in a Particular Stage */
#define ANOMALY_05000285 /* New Feature: EMAC TX DMA Word Alignment
* (Not Available On Older Silicon) */
#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */
#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously
* On Next System MMR Access */
#define ANOMALY_05000316 /* EMAC RMII mode: collisions occur in Full Duplex
* mode */
#define ANOMALY_05000321 /* EMAC RMII mode: TX frames in half duplex fail with
* status No Carrier */
#endif /* CONFIG_BF_REV_0_2 */
#endif /* _MACH_ANOMALY_H_ */

27
include/asm-blackfin/mach-common/cdef_LPBlackfin.h
View File

@ -39,7 +39,20 @@
#define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS)
#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val)
#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
#ifdef ANOMALY_05000125
static __inline__ void bfin_write_DMEM_CONTROL(unsigned int val)
{
unsigned long flags, iwr;
local_irq_save(flags);
__asm__(".align 8\n");
bfin_write32(IMEM_CONTROL, val);
__builtin_bfin_ssync();
local_irq_restore(flags);
}
#else
#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
#endif
#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val)
#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR)
@ -125,7 +138,21 @@
#define DTEST_DATA3 0xFFE0040C
*/
#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
#ifdef ANOMALY_05000125
static __inline__ void bfin_write_IMEM_CONTROL(unsigned int val)
{
unsigned long flags, iwr;
local_irq_save(flags);
__asm__(".align 8\n");
bfin_write32(IMEM_CONTROL, val);
__builtin_bfin_ssync();
local_irq_restore(flags);
}
#else
#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val)
#endif
#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val)
#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR)