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ARM: dts: hisilicon: fix errors detected by spi-pl022.yaml 

1. Change clock-names to "sspclk", "apb_pclk". Both of them use the same
   clock.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
zero-sugar-mainline-defconfig
Zhen Lei 2020-10-12 14:12:22 +08:00 committed by Wei Xu
parent 05484c171d
commit 4c246408f0
1 changed files with 6 additions and 6 deletions
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12
arch/arm/boot/dts/hi3519.dtsi
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@ -127,8 +127,8 @@
compatible = "arm,pl022", "arm,primecell";
reg = <0x12120000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_SPI0_CLK>;
clock-names = "apb_pclk";
clocks = <&crg HI3519_SPI0_CLK>, <&crg HI3519_SPI0_CLK>;
clock-names = "sspclk", "apb_pclk";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@ -139,8 +139,8 @@
compatible = "arm,pl022", "arm,primecell";
reg = <0x12121000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_SPI1_CLK>;
clock-names = "apb_pclk";
clocks = <&crg HI3519_SPI1_CLK>, <&crg HI3519_SPI1_CLK>;
clock-names = "sspclk", "apb_pclk";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@ -151,8 +151,8 @@
compatible = "arm,pl022", "arm,primecell";
reg = <0x12122000 0x1000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_SPI2_CLK>;
clock-names = "apb_pclk";
clocks = <&crg HI3519_SPI2_CLK>, <&crg HI3519_SPI2_CLK>;
clock-names = "sspclk", "apb_pclk";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;