ASoC: da7213: Refactor sysclk(), pll() functions to improve handling
Currently the handling of the PLL in the driver is a little clunky, and not ideal for all modes. This patch updates the code to make it cleaner and more sensible for the various PLL states. Key items of note are: - MCLK squaring is now handled directly as part of the sysclk() function, removing the need for a private flag to set this feature. - All PLL modes are defined as an enum, and are handled as a case statement in pll() function to clean up configuration. This also removes any need for a private flag for SRM. - For 32KHz mode, checks are made on codec master mode and correct MCLK rates, to avoid incorrect usage of PLL for this operation. - For 32KHz mode, SRM flag now correctly enabled and fout set to sensible value to achieve appropriate PLL dividers. Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com> Signed-off-by: Mark Brown <broonie@kernel.org>hifive-unleashed-5.1
Adam Thomson
Mark Brown
parent
f612680fb5
commit
4c75225aa0
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@ -1297,10 +1297,13 @@ static int da7213_set_dai_sysclk(struct snd_soc_dai *codec_dai,
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switch (clk_id) {
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case DA7213_CLKSRC_MCLK:
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da7213->mclk_squarer_en = false;
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snd_soc_update_bits(codec, DA7213_PLL_CTRL,
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DA7213_PLL_MCLK_SQR_EN, 0);
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break;
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case DA7213_CLKSRC_MCLK_SQR:
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da7213->mclk_squarer_en = true;
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snd_soc_update_bits(codec, DA7213_PLL_CTRL,
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DA7213_PLL_MCLK_SQR_EN,
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DA7213_PLL_MCLK_SQR_EN);
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break;
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default:
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dev_err(codec_dai->dev, "Unknown clock source %d\n", clk_id);
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@ -1324,7 +1327,7 @@ static int da7213_set_dai_sysclk(struct snd_soc_dai *codec_dai,
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return 0;
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}
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/* Supported PLL input frequencies are 5MHz - 54MHz. */
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/* Supported PLL input frequencies are 32KHz, 5MHz - 54MHz. */
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static int da7213_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
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int source, unsigned int fref, unsigned int fout)
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{
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@ -1336,22 +1339,26 @@ static int da7213_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
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u32 freq_ref;
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u64 frac_div;
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/* Reset PLL configuration */
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snd_soc_write(codec, DA7213_PLL_CTRL, 0);
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pll_ctrl = 0;
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/* Workout input divider based on MCLK rate */
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if (da7213->mclk_rate == 32768) {
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if (!da7213->master) {
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dev_err(codec->dev,
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"32KHz only valid if codec is clock master\n");
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return -EINVAL;
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}
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/* 32KHz PLL Mode */
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indiv_bits = DA7213_PLL_INDIV_9_TO_18_MHZ;
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indiv = DA7213_PLL_INDIV_9_TO_18_MHZ_VAL;
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source = DA7213_SYSCLK_PLL_32KHZ;
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freq_ref = 3750000;
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pll_ctrl |= DA7213_PLL_32K_MODE;
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} else {
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/* 5 - 54MHz MCLK */
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if (da7213->mclk_rate < 5000000) {
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goto pll_err;
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dev_err(codec->dev,
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"PLL input clock %d below valid range\n",
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da7213->mclk_rate);
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return -EINVAL;
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} else if (da7213->mclk_rate <= 9000000) {
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indiv_bits = DA7213_PLL_INDIV_5_TO_9_MHZ;
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indiv = DA7213_PLL_INDIV_5_TO_9_MHZ_VAL;
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@ -1365,31 +1372,43 @@ static int da7213_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
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indiv_bits = DA7213_PLL_INDIV_36_TO_54_MHZ;
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indiv = DA7213_PLL_INDIV_36_TO_54_MHZ_VAL;
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} else {
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goto pll_err;
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dev_err(codec->dev,
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"PLL input clock %d above valid range\n",
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da7213->mclk_rate);
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return -EINVAL;
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}
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freq_ref = (da7213->mclk_rate / indiv);
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}
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pll_ctrl |= indiv_bits;
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pll_ctrl = indiv_bits;
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/* PLL Bypass mode */
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if (source == DA7213_SYSCLK_MCLK) {
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snd_soc_write(codec, DA7213_PLL_CTRL, pll_ctrl);
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/* Configure PLL */
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switch (source) {
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case DA7213_SYSCLK_MCLK:
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snd_soc_update_bits(codec, DA7213_PLL_CTRL,
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DA7213_PLL_INDIV_MASK |
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DA7213_PLL_MODE_MASK, pll_ctrl);
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return 0;
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}
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/*
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* If Codec is slave and SRM enabled,
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* freq_out is (98304000 + 90316800)/2 = 94310400
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*/
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if (!da7213->master && da7213->srm_en) {
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fout = DA7213_PLL_FREQ_OUT_94310400;
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case DA7213_SYSCLK_PLL:
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break;
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case DA7213_SYSCLK_PLL_SRM:
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pll_ctrl |= DA7213_PLL_SRM_EN;
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}
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fout = DA7213_PLL_FREQ_OUT_94310400;
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break;
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case DA7213_SYSCLK_PLL_32KHZ:
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if (da7213->mclk_rate != 32768) {
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dev_err(codec->dev,
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"32KHz mode only valid with 32KHz MCLK\n");
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return -EINVAL;
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}
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/* Enable MCLK squarer if required */
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if (da7213->mclk_squarer_en)
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pll_ctrl |= DA7213_PLL_MCLK_SQR_EN;
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pll_ctrl |= DA7213_PLL_32K_MODE | DA7213_PLL_SRM_EN;
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fout = DA7213_PLL_FREQ_OUT_94310400;
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break;
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default:
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dev_err(codec->dev, "Invalid PLL config\n");
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return -EINVAL;
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}
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/* Calculate dividers for PLL */
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pll_integer = fout / freq_ref;
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@ -1405,14 +1424,11 @@ static int da7213_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
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/* Enable PLL */
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pll_ctrl |= DA7213_PLL_EN;
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snd_soc_write(codec, DA7213_PLL_CTRL, pll_ctrl);
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snd_soc_update_bits(codec, DA7213_PLL_CTRL,
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DA7213_PLL_INDIV_MASK | DA7213_PLL_MODE_MASK,
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pll_ctrl);
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return 0;
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pll_err:
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dev_err(codec_dai->dev, "Unsupported PLL input frequency %d\n",
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da7213->mclk_rate);
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return -EINVAL;
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}
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/* DAI operations */
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@ -1607,9 +1623,6 @@ static int da7213_probe(struct snd_soc_codec *codec)
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DA7213_ALC_CALIB_MODE_MAN, 0);
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da7213->alc_calib_auto = true;
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/* Default to using SRM for slave mode */
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da7213->srm_en = true;
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/* Default PC counter to free-running */
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snd_soc_update_bits(codec, DA7213_PC_COUNT, DA7213_PC_FREERUN_MASK,
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DA7213_PC_FREERUN_MASK);
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@ -172,6 +172,7 @@
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#define DA7213_PLL_32K_MODE (0x1 << 5)
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#define DA7213_PLL_SRM_EN (0x1 << 6)
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#define DA7213_PLL_EN (0x1 << 7)
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#define DA7213_PLL_MODE_MASK (0x7 << 5)
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/* DA7213_DAI_CLK_MODE = 0x28 */
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#define DA7213_DAI_BCLKS_PER_WCLK_32 (0x0 << 0)
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@ -499,8 +500,6 @@
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#define DA7213_ALC_AVG_ITERATIONS 5
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/* PLL related */
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#define DA7213_SYSCLK_MCLK 0
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#define DA7213_SYSCLK_PLL 1
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#define DA7213_PLL_FREQ_OUT_90316800 90316800
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#define DA7213_PLL_FREQ_OUT_98304000 98304000
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#define DA7213_PLL_FREQ_OUT_94310400 94310400
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@ -515,6 +514,13 @@ enum da7213_clk_src {
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DA7213_CLKSRC_MCLK_SQR,
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};
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enum da7213_sys_clk {
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DA7213_SYSCLK_MCLK = 0,
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DA7213_SYSCLK_PLL,
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DA7213_SYSCLK_PLL_SRM,
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DA7213_SYSCLK_PLL_32KHZ
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};
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/* Codec private data */
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struct da7213_priv {
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struct regmap *regmap;
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@ -522,8 +528,6 @@ struct da7213_priv {
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unsigned int mclk_rate;
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int clk_src;
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bool master;
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bool mclk_squarer_en;
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bool srm_en;
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bool alc_calib_auto;
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bool alc_en;
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struct da7213_platform_data *pdata;
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