ath5k: Fix reset and interrupts for AHB type of devices.
On WiSoc we cannot access mac register before it is resetted. It will crash hardware otherwise. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: Wojciech Dubowik <Wojciech.Dubowik@neratec.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -2148,7 +2148,8 @@ ath5k_intr(int irq, void *dev_id)
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unsigned int counter = 1000;
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if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
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!ath5k_hw_is_intr_pending(ah)))
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((ath5k_get_bus_type(ah) != ATH_AHB) &&
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!ath5k_hw_is_intr_pending(ah))))
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return IRQ_NONE;
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do {
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@ -2214,6 +2215,10 @@ ath5k_intr(int irq, void *dev_id)
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tasklet_schedule(&sc->rf_kill.toggleq);
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}
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if (ath5k_get_bus_type(ah) == ATH_AHB)
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break;
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} while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
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if (unlikely(!counter))
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@ -27,6 +27,7 @@
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#include <linux/pci.h> /* To determine if a card is pci-e */
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#include <linux/log2.h>
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#include <linux/platform_device.h>
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#include "ath5k.h"
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#include "reg.h"
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#include "base.h"
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@ -141,7 +142,9 @@ static void ath5k_hw_init_core_clock(struct ath5k_hw *ah)
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/* Set 32MHz USEC counter */
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if ((ah->ah_radio == AR5K_RF5112) ||
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(ah->ah_radio == AR5K_RF5413))
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(ah->ah_radio == AR5K_RF5413) ||
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(ah->ah_radio == AR5K_RF2316) ||
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(ah->ah_radio == AR5K_RF2317))
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/* Remain on 40MHz clock ? */
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sclock = 40 - 1;
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else
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@ -244,6 +247,7 @@ static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
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if ((ah->ah_radio == AR5K_RF5112) ||
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(ah->ah_radio == AR5K_RF5413) ||
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(ah->ah_radio == AR5K_RF2316) ||
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(ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
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spending = 0x14;
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else
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@ -299,6 +303,7 @@ static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
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if ((ah->ah_radio == AR5K_RF5112) ||
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(ah->ah_radio == AR5K_RF5413) ||
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(ah->ah_radio == AR5K_RF2316) ||
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(ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
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spending = 0x14;
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else
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@ -357,6 +362,64 @@ static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
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return ret;
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}
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/*
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* Reset AHB chipset
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* AR5K_RESET_CTL_PCU flag resets WMAC
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* AR5K_RESET_CTL_BASEBAND flag resets WBB
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*/
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static int ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
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{
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u32 mask = flags ? flags : ~0U;
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volatile u32 *reg;
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u32 regval;
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u32 val = 0;
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/* ah->ah_mac_srev is not available at this point yet */
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if (ah->ah_sc->devid >= AR5K_SREV_AR2315_R6) {
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reg = (u32 *) AR5K_AR2315_RESET;
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if (mask & AR5K_RESET_CTL_PCU)
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val |= AR5K_AR2315_RESET_WMAC;
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if (mask & AR5K_RESET_CTL_BASEBAND)
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val |= AR5K_AR2315_RESET_BB_WARM;
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} else {
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reg = (u32 *) AR5K_AR5312_RESET;
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if (to_platform_device(ah->ah_sc->dev)->id == 0) {
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if (mask & AR5K_RESET_CTL_PCU)
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val |= AR5K_AR5312_RESET_WMAC0;
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if (mask & AR5K_RESET_CTL_BASEBAND)
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val |= AR5K_AR5312_RESET_BB0_COLD |
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AR5K_AR5312_RESET_BB0_WARM;
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} else {
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if (mask & AR5K_RESET_CTL_PCU)
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val |= AR5K_AR5312_RESET_WMAC1;
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if (mask & AR5K_RESET_CTL_BASEBAND)
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val |= AR5K_AR5312_RESET_BB1_COLD |
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AR5K_AR5312_RESET_BB1_WARM;
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}
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}
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/* Put BB/MAC into reset */
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regval = __raw_readl(reg);
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__raw_writel(regval | val, reg);
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regval = __raw_readl(reg);
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udelay(100);
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/* Bring BB/MAC out of reset */
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__raw_writel(regval & ~val, reg);
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regval = __raw_readl(reg);
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/*
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* Reset configuration register (for hw byte-swap). Note that this
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* is only set for big endian. We do the necessary magic in
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* AR5K_INIT_CFG.
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*/
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if ((flags & AR5K_RESET_CTL_PCU) == 0)
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ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
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return 0;
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}
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/*
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* Sleep control
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*/
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@ -456,6 +519,9 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
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u32 bus_flags;
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int ret;
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if (ath5k_get_bus_type(ah) == ATH_AHB)
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return 0;
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/* Make sure device is awake */
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ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
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if (ret) {
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@ -511,11 +577,13 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
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mode = 0;
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clock = 0;
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/* Wakeup the device */
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ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
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if (ret) {
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ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
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return ret;
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if ((ath5k_get_bus_type(ah) != ATH_AHB) || !initial) {
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/* Wakeup the device */
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ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
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if (ret) {
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ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
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return ret;
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}
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}
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/*
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@ -534,8 +602,12 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
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AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
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mdelay(2);
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} else {
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ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
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AR5K_RESET_CTL_BASEBAND | bus_flags);
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if (ath5k_get_bus_type(ah) == ATH_AHB)
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ret = ath5k_hw_wisoc_reset(ah, AR5K_RESET_CTL_PCU |
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AR5K_RESET_CTL_BASEBAND);
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else
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ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
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AR5K_RESET_CTL_BASEBAND | bus_flags);
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}
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if (ret) {
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@ -550,9 +622,15 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
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return ret;
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}
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/* ...clear reset control register and pull device out of
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* warm reset */
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if (ath5k_hw_nic_reset(ah, 0)) {
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/* ...reset configuration regiter on Wisoc ...
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* ...clear reset control register and pull device out of
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* warm reset on others */
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if (ath5k_get_bus_type(ah) == ATH_AHB)
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ret = ath5k_hw_wisoc_reset(ah, 0);
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else
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ret = ath5k_hw_nic_reset(ah, 0);
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if (ret) {
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ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
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return -EIO;
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}
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@ -708,7 +786,8 @@ static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
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/* Set fast ADC */
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if ((ah->ah_radio == AR5K_RF5413) ||
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(ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
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(ah->ah_radio == AR5K_RF2317) ||
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(ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
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u32 fast_adc = true;
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if (channel->center_freq == 2462 ||
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