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drm/i915: Rework plane readout. 

All non-primary planes get disabled during hw readout,
this reduces complexity and means not having to do some plane
visibility checks during the first commit.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
hifive-unleashed-5.1
Maarten Lankhorst 2015-07-13 16:30:20 +02:00 committed by Daniel Vetter
parent 3bbaba0cea
commit 4cf0ebbd4f
3 changed files with 8 additions and 86 deletions
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7
drivers/gpu/drm/i915/intel_atomic.c
View File

@ -98,13 +98,6 @@ int intel_atomic_check(struct drm_device *dev,
return -EINVAL;
}
if (crtc_state &&
crtc_state->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES) {
ret = drm_atomic_add_affected_planes(state, &nuclear_crtc->base);
if (ret)
return ret;
}
ret = drm_atomic_helper_check_planes(dev, state);
if (ret)
return ret;

86
drivers/gpu/drm/i915/intel_display.c
View File

@ -11781,34 +11781,6 @@ static bool check_encoder_cloning(struct drm_atomic_state *state,
return true;
}
static void intel_crtc_check_initial_planes(struct drm_crtc *crtc,
struct drm_crtc_state *crtc_state)
{
struct intel_crtc_state *pipe_config =
to_intel_crtc_state(crtc_state);
struct drm_plane *p;
unsigned visible_mask = 0;
drm_for_each_plane_mask(p, crtc->dev, crtc_state->plane_mask) {
struct drm_plane_state *plane_state =
drm_atomic_get_existing_plane_state(crtc_state->state, p);
if (WARN_ON(!plane_state))
continue;
if (!plane_state->fb)
crtc_state->plane_mask &=
~(1 << drm_plane_index(p));
else if (to_intel_plane_state(plane_state)->visible)
visible_mask |= 1 << drm_plane_index(p);
}
if (!visible_mask)
return;
pipe_config->quirks &= ~PIPE_CONFIG_QUIRK_INITIAL_PLANES;
}
static int intel_crtc_atomic_check(struct drm_crtc *crtc,
struct drm_crtc_state *crtc_state)
{
@ -11830,10 +11802,6 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
"[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
idx, crtc->state->active, intel_crtc->active);
/* plane mask is fixed up after all initial planes are calculated */
if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES)
intel_crtc_check_initial_planes(crtc, crtc_state);
if (mode_changed && !crtc_state->active)
intel_crtc->atomic.update_wm_post = true;
@ -13186,19 +13154,6 @@ intel_modeset_compute_config(struct drm_atomic_state *state)
continue;
}
if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES) {
ret = drm_atomic_add_affected_planes(state, crtc);
if (ret)
return ret;
/*
* We ought to handle i915.fastboot here.
* If no modeset is required and the primary plane has
* a fb, update the members of crtc_state as needed,
* and run the necessary updates during vblank evasion.
*/
}
modeset = needs_modeset(crtc_state);
recalc = pipe_config->quirks & PIPE_CONFIG_QUIRK_INHERITED_MODE;
@ -15456,47 +15411,22 @@ static void readout_plane_state(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state)
{
struct intel_plane *p;
struct drm_plane_state *drm_plane_state;
struct intel_plane_state *plane_state;
bool active = crtc_state->base.active;
if (active) {
crtc_state->quirks |= PIPE_CONFIG_QUIRK_INITIAL_PLANES;
/* apply to previous sw state too */
to_intel_crtc_state(crtc->base.state)->quirks |=
PIPE_CONFIG_QUIRK_INITIAL_PLANES;
}
for_each_intel_plane(crtc->base.dev, p) {
bool visible = active;
if (crtc->pipe != p->pipe)
continue;
drm_plane_state = p->base.state;
plane_state = to_intel_plane_state(p->base.state);
/* Plane scaler state is not touched here. The first atomic
* commit will restore all plane scalers to its old state.
*/
if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
plane_state->visible = primary_get_hw_state(crtc);
else {
if (active)
p->disable_plane(&p->base, &crtc->base);
if (active && p->base.type == DRM_PLANE_TYPE_PRIMARY) {
visible = primary_get_hw_state(crtc);
to_intel_plane_state(drm_plane_state)->visible = visible;
} else {
/*
* unknown state, assume it's off to force a transition
* to on when calculating state changes.
*/
to_intel_plane_state(drm_plane_state)->visible = false;
}
if (visible) {
crtc_state->base.plane_mask |=
1 << drm_plane_index(&p->base);
} else if (crtc_state->base.state) {
/* Make this unconditional for atomic hw readout. */
crtc_state->base.plane_mask &=
~(1 << drm_plane_index(&p->base));
plane_state->visible = false;
}
}
}

1
drivers/gpu/drm/i915/intel_drv.h
View File

@ -341,7 +341,6 @@ struct intel_crtc_state {
*/
#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
#define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
#define PIPE_CONFIG_QUIRK_INITIAL_PLANES (1<<2) /* planes are in unknown state */
unsigned long quirks;
/* Pipe source size (ie. panel fitter input size)