drm/i915: Rework plane readout.
All non-primary planes get disabled during hw readout, this reduces complexity and means not having to do some plane visibility checks during the first commit. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Daniel Stone <daniels@collabora.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -98,13 +98,6 @@ int intel_atomic_check(struct drm_device *dev,
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return -EINVAL;
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return -EINVAL;
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}
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}
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if (crtc_state &&
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crtc_state->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES) {
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ret = drm_atomic_add_affected_planes(state, &nuclear_crtc->base);
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if (ret)
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return ret;
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}
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ret = drm_atomic_helper_check_planes(dev, state);
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ret = drm_atomic_helper_check_planes(dev, state);
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if (ret)
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if (ret)
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return ret;
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return ret;
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@ -11781,34 +11781,6 @@ static bool check_encoder_cloning(struct drm_atomic_state *state,
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return true;
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return true;
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}
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}
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static void intel_crtc_check_initial_planes(struct drm_crtc *crtc,
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struct drm_crtc_state *crtc_state)
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{
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struct intel_crtc_state *pipe_config =
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to_intel_crtc_state(crtc_state);
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struct drm_plane *p;
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unsigned visible_mask = 0;
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drm_for_each_plane_mask(p, crtc->dev, crtc_state->plane_mask) {
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struct drm_plane_state *plane_state =
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drm_atomic_get_existing_plane_state(crtc_state->state, p);
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if (WARN_ON(!plane_state))
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continue;
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if (!plane_state->fb)
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crtc_state->plane_mask &=
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~(1 << drm_plane_index(p));
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else if (to_intel_plane_state(plane_state)->visible)
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visible_mask |= 1 << drm_plane_index(p);
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}
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if (!visible_mask)
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return;
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pipe_config->quirks &= ~PIPE_CONFIG_QUIRK_INITIAL_PLANES;
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}
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static int intel_crtc_atomic_check(struct drm_crtc *crtc,
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static int intel_crtc_atomic_check(struct drm_crtc *crtc,
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struct drm_crtc_state *crtc_state)
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struct drm_crtc_state *crtc_state)
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{
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{
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@ -11830,10 +11802,6 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
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"[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
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"[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
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idx, crtc->state->active, intel_crtc->active);
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idx, crtc->state->active, intel_crtc->active);
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/* plane mask is fixed up after all initial planes are calculated */
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if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES)
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intel_crtc_check_initial_planes(crtc, crtc_state);
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if (mode_changed && !crtc_state->active)
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if (mode_changed && !crtc_state->active)
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intel_crtc->atomic.update_wm_post = true;
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intel_crtc->atomic.update_wm_post = true;
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@ -13186,19 +13154,6 @@ intel_modeset_compute_config(struct drm_atomic_state *state)
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continue;
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continue;
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}
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}
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if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES) {
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ret = drm_atomic_add_affected_planes(state, crtc);
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if (ret)
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return ret;
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/*
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* We ought to handle i915.fastboot here.
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* If no modeset is required and the primary plane has
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* a fb, update the members of crtc_state as needed,
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* and run the necessary updates during vblank evasion.
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*/
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}
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modeset = needs_modeset(crtc_state);
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modeset = needs_modeset(crtc_state);
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recalc = pipe_config->quirks & PIPE_CONFIG_QUIRK_INHERITED_MODE;
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recalc = pipe_config->quirks & PIPE_CONFIG_QUIRK_INHERITED_MODE;
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@ -15456,47 +15411,22 @@ static void readout_plane_state(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state)
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struct intel_crtc_state *crtc_state)
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{
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{
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struct intel_plane *p;
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struct intel_plane *p;
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struct drm_plane_state *drm_plane_state;
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struct intel_plane_state *plane_state;
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bool active = crtc_state->base.active;
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bool active = crtc_state->base.active;
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if (active) {
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crtc_state->quirks |= PIPE_CONFIG_QUIRK_INITIAL_PLANES;
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/* apply to previous sw state too */
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to_intel_crtc_state(crtc->base.state)->quirks |=
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PIPE_CONFIG_QUIRK_INITIAL_PLANES;
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}
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for_each_intel_plane(crtc->base.dev, p) {
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for_each_intel_plane(crtc->base.dev, p) {
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bool visible = active;
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if (crtc->pipe != p->pipe)
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if (crtc->pipe != p->pipe)
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continue;
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continue;
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drm_plane_state = p->base.state;
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plane_state = to_intel_plane_state(p->base.state);
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/* Plane scaler state is not touched here. The first atomic
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if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
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* commit will restore all plane scalers to its old state.
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plane_state->visible = primary_get_hw_state(crtc);
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*/
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else {
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if (active)
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p->disable_plane(&p->base, &crtc->base);
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if (active && p->base.type == DRM_PLANE_TYPE_PRIMARY) {
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plane_state->visible = false;
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visible = primary_get_hw_state(crtc);
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to_intel_plane_state(drm_plane_state)->visible = visible;
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} else {
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/*
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* unknown state, assume it's off to force a transition
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* to on when calculating state changes.
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*/
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to_intel_plane_state(drm_plane_state)->visible = false;
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}
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if (visible) {
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crtc_state->base.plane_mask |=
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1 << drm_plane_index(&p->base);
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} else if (crtc_state->base.state) {
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/* Make this unconditional for atomic hw readout. */
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crtc_state->base.plane_mask &=
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~(1 << drm_plane_index(&p->base));
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}
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}
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}
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}
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}
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}
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@ -341,7 +341,6 @@ struct intel_crtc_state {
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*/
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*/
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#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
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#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
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#define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
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#define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
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#define PIPE_CONFIG_QUIRK_INITIAL_PLANES (1<<2) /* planes are in unknown state */
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unsigned long quirks;
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unsigned long quirks;
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/* Pipe source size (ie. panel fitter input size)
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/* Pipe source size (ie. panel fitter input size)
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