usb: dwc3: core.h: add some register definitions
Add OTG and GHWPARAMS6 register definitions Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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@ -201,6 +201,15 @@
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#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
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#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
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/* Global Status Register */
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#define DWC3_GSTS_OTG_IP BIT(10)
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#define DWC3_GSTS_BC_IP BIT(9)
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#define DWC3_GSTS_ADP_IP BIT(8)
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#define DWC3_GSTS_HOST_IP BIT(7)
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#define DWC3_GSTS_DEVICE_IP BIT(6)
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#define DWC3_GSTS_CSR_TIMEOUT BIT(5)
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#define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4)
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/* Global USB2 PHY Configuration Register */
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#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31)
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#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30)
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@ -286,6 +295,11 @@
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#define DWC3_MAX_HIBER_SCRATCHBUFS 15
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/* Global HWPARAMS6 Register */
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#define DWC3_GHWPARAMS6_BCSUPPORT BIT(14)
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#define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13)
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#define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12)
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#define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11)
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#define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10)
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#define DWC3_GHWPARAMS6_EN_FPGA BIT(7)
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/* Global HWPARAMS7 Register */
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@ -467,6 +481,74 @@
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#define DWC3_DEV_IMOD_INTERVAL_SHIFT 0
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#define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0)
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/* OTG Configuration Register */
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#define DWC3_OCFG_DISPWRCUTTOFF BIT(5)
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#define DWC3_OCFG_HIBDISMASK BIT(4)
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#define DWC3_OCFG_SFTRSTMASK BIT(3)
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#define DWC3_OCFG_OTGVERSION BIT(2)
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#define DWC3_OCFG_HNPCAP BIT(1)
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#define DWC3_OCFG_SRPCAP BIT(0)
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/* OTG CTL Register */
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#define DWC3_OCTL_OTG3GOERR BIT(7)
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#define DWC3_OCTL_PERIMODE BIT(6)
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#define DWC3_OCTL_PRTPWRCTL BIT(5)
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#define DWC3_OCTL_HNPREQ BIT(4)
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#define DWC3_OCTL_SESREQ BIT(3)
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#define DWC3_OCTL_TERMSELIDPULSE BIT(2)
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#define DWC3_OCTL_DEVSETHNPEN BIT(1)
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#define DWC3_OCTL_HSTSETHNPEN BIT(0)
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/* OTG Event Register */
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#define DWC3_OEVT_DEVICEMODE BIT(31)
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#define DWC3_OEVT_XHCIRUNSTPSET BIT(27)
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#define DWC3_OEVT_DEVRUNSTPSET BIT(26)
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#define DWC3_OEVT_HIBENTRY BIT(25)
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#define DWC3_OEVT_CONIDSTSCHNG BIT(24)
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#define DWC3_OEVT_HRRCONFNOTIF BIT(23)
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#define DWC3_OEVT_HRRINITNOTIF BIT(22)
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#define DWC3_OEVT_ADEVIDLE BIT(21)
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#define DWC3_OEVT_ADEVBHOSTEND BIT(20)
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#define DWC3_OEVT_ADEVHOST BIT(19)
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#define DWC3_OEVT_ADEVHNPCHNG BIT(18)
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#define DWC3_OEVT_ADEVSRPDET BIT(17)
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#define DWC3_OEVT_ADEVSESSENDDET BIT(16)
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#define DWC3_OEVT_BDEVBHOSTEND BIT(11)
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#define DWC3_OEVT_BDEVHNPCHNG BIT(10)
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#define DWC3_OEVT_BDEVSESSVLDDET BIT(9)
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#define DWC3_OEVT_BDEVVBUSCHNG BIT(8)
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#define DWC3_OEVT_BSESSVLD BIT(3)
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#define DWC3_OEVT_HSTNEGSTS BIT(2)
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#define DWC3_OEVT_SESREQSTS BIT(1)
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#define DWC3_OEVT_ERROR BIT(0)
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/* OTG Event Enable Register */
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#define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27)
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#define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26)
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#define DWC3_OEVTEN_HIBENTRYEN BIT(25)
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#define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24)
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#define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23)
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#define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22)
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#define DWC3_OEVTEN_ADEVIDLEEN BIT(21)
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#define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20)
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#define DWC3_OEVTEN_ADEVHOSTEN BIT(19)
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#define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18)
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#define DWC3_OEVTEN_ADEVSRPDETEN BIT(17)
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#define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16)
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#define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11)
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#define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10)
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#define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9)
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#define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8)
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/* OTG Status Register */
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#define DWC3_OSTS_DEVRUNSTP BIT(13)
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#define DWC3_OSTS_XHCIRUNSTP BIT(12)
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#define DWC3_OSTS_PERIPHERALSTATE BIT(4)
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#define DWC3_OSTS_XHCIPRTPOWER BIT(3)
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#define DWC3_OSTS_BSESVLD BIT(2)
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#define DWC3_OSTS_VBUSVLD BIT(1)
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#define DWC3_OSTS_CONIDSTS BIT(0)
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/* Structures */
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struct dwc3_trb;
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