redonkable/alistair23-linux
redonkable/alistair23-linux
1
0
Fork 0
Code Releases Activity

usb: dwc3: core.h: add some register definitions

Browse source 
Add OTG and GHWPARAMS6 register definitions

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
This commit is contained in:
Roger Quadros 2018-02-27 13:29:11 +02:00 committed by Felipe Balbi
parent e8284db48f
commit 4cff75c7fe
1 changed files with 82 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

82
drivers/usb/dwc3/core.h
View file

@ -201,6 +201,15 @@
#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
/* Global Status Register */
#define DWC3_GSTS_OTG_IP BIT(10)
#define DWC3_GSTS_BC_IP BIT(9)
#define DWC3_GSTS_ADP_IP BIT(8)
#define DWC3_GSTS_HOST_IP BIT(7)
#define DWC3_GSTS_DEVICE_IP BIT(6)
#define DWC3_GSTS_CSR_TIMEOUT BIT(5)
#define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4)
/* Global USB2 PHY Configuration Register */
#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31)
#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30)
@ -286,6 +295,11 @@
#define DWC3_MAX_HIBER_SCRATCHBUFS 15
/* Global HWPARAMS6 Register */
#define DWC3_GHWPARAMS6_BCSUPPORT BIT(14)
#define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13)
#define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12)
#define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11)
#define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10)
#define DWC3_GHWPARAMS6_EN_FPGA BIT(7)
/* Global HWPARAMS7 Register */
@ -467,6 +481,74 @@
#define DWC3_DEV_IMOD_INTERVAL_SHIFT 0
#define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0)
/* OTG Configuration Register */
#define DWC3_OCFG_DISPWRCUTTOFF BIT(5)
#define DWC3_OCFG_HIBDISMASK BIT(4)
#define DWC3_OCFG_SFTRSTMASK BIT(3)
#define DWC3_OCFG_OTGVERSION BIT(2)
#define DWC3_OCFG_HNPCAP BIT(1)
#define DWC3_OCFG_SRPCAP BIT(0)
/* OTG CTL Register */
#define DWC3_OCTL_OTG3GOERR BIT(7)
#define DWC3_OCTL_PERIMODE BIT(6)
#define DWC3_OCTL_PRTPWRCTL BIT(5)
#define DWC3_OCTL_HNPREQ BIT(4)
#define DWC3_OCTL_SESREQ BIT(3)
#define DWC3_OCTL_TERMSELIDPULSE BIT(2)
#define DWC3_OCTL_DEVSETHNPEN BIT(1)
#define DWC3_OCTL_HSTSETHNPEN BIT(0)
/* OTG Event Register */
#define DWC3_OEVT_DEVICEMODE BIT(31)
#define DWC3_OEVT_XHCIRUNSTPSET BIT(27)
#define DWC3_OEVT_DEVRUNSTPSET BIT(26)
#define DWC3_OEVT_HIBENTRY BIT(25)
#define DWC3_OEVT_CONIDSTSCHNG BIT(24)
#define DWC3_OEVT_HRRCONFNOTIF BIT(23)
#define DWC3_OEVT_HRRINITNOTIF BIT(22)
#define DWC3_OEVT_ADEVIDLE BIT(21)
#define DWC3_OEVT_ADEVBHOSTEND BIT(20)
#define DWC3_OEVT_ADEVHOST BIT(19)
#define DWC3_OEVT_ADEVHNPCHNG BIT(18)
#define DWC3_OEVT_ADEVSRPDET BIT(17)
#define DWC3_OEVT_ADEVSESSENDDET BIT(16)
#define DWC3_OEVT_BDEVBHOSTEND BIT(11)
#define DWC3_OEVT_BDEVHNPCHNG BIT(10)
#define DWC3_OEVT_BDEVSESSVLDDET BIT(9)
#define DWC3_OEVT_BDEVVBUSCHNG BIT(8)
#define DWC3_OEVT_BSESSVLD BIT(3)
#define DWC3_OEVT_HSTNEGSTS BIT(2)
#define DWC3_OEVT_SESREQSTS BIT(1)
#define DWC3_OEVT_ERROR BIT(0)
/* OTG Event Enable Register */
#define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27)
#define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26)
#define DWC3_OEVTEN_HIBENTRYEN BIT(25)
#define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24)
#define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23)
#define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22)
#define DWC3_OEVTEN_ADEVIDLEEN BIT(21)
#define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20)
#define DWC3_OEVTEN_ADEVHOSTEN BIT(19)
#define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18)
#define DWC3_OEVTEN_ADEVSRPDETEN BIT(17)
#define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16)
#define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11)
#define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10)
#define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9)
#define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8)
/* OTG Status Register */
#define DWC3_OSTS_DEVRUNSTP BIT(13)
#define DWC3_OSTS_XHCIRUNSTP BIT(12)
#define DWC3_OSTS_PERIPHERALSTATE BIT(4)
#define DWC3_OSTS_XHCIPRTPOWER BIT(3)
#define DWC3_OSTS_BSESVLD BIT(2)
#define DWC3_OSTS_VBUSVLD BIT(1)
#define DWC3_OSTS_CONIDSTS BIT(0)
/* Structures */
struct dwc3_trb;