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ARM: 6512/1: perf: fix warnings generated by sparse

Russell reported a number of warnings coming from sparse when
checking the ARM perf_event.c files:

| perf_event.c seems to also have problems too:
|
|   CHECK   arch/arm/kernel/perf_event.c
|   arch/arm/kernel/perf_event.c:37:1: warning: symbol 'pmu_lock' was not declared. Should it be static?
|   arch/arm/kernel/perf_event.c:70:1: warning: symbol 'cpu_hw_events' was not declared. Should it be static?
|   arch/arm/kernel/perf_event.c:1006:1: warning: symbol 'armv6pmu_enable_event' was not declared. Should it be static?
|   arch/arm/kernel/perf_event.c:1113:1: warning: symbol 'armv6pmu_stop' was not declared. Should it be static?
|   arch/arm/kernel/perf_event.c:1956:6: warning: symbol 'armv7pmu_enable_event' was not declared. Should it be static?
|   arch/arm/kernel/perf_event.c:3072:14: warning: incorrect type in argument 1 (different address spaces)
|   arch/arm/kernel/perf_event.c:3072:14:    expected void const volatile [noderef] <asn:1>*<noident>
|   arch/arm/kernel/perf_event.c:3072:14:    got struct frame_tail *tail
|   arch/arm/kernel/perf_event.c:3074:49: warning: incorrect type in argument 2 (different address spaces)
|   arch/arm/kernel/perf_event.c:3074:49:    expected void const [noderef] <asn:1>*from
|   arch/arm/kernel/perf_event.c:3074:49:    got struct frame_tail *tail

This patch resolves these issues so we can live in silence
again.

Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
hifive-unleashed-5.1
Will Deacon 2010-11-30 18:15:53 +01:00 committed by Russell King
parent 83cf1eecfe
commit 4d6b7a779b
4 changed files with 23 additions and 23 deletions

View File

@ -32,7 +32,7 @@ static struct platform_device *pmu_device;
* Hardware lock to serialize accesses to PMU registers. Needed for the
* read/modify/write sequences.
*/
DEFINE_SPINLOCK(pmu_lock);
static DEFINE_SPINLOCK(pmu_lock);
/*
* ARMv6 supports a maximum of 3 events, starting from index 1. If we add
@ -65,7 +65,7 @@ struct cpu_hw_events {
*/
unsigned long active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
};
DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
struct arm_pmu {
enum arm_perf_pmu_ids id;
@ -673,17 +673,17 @@ arch_initcall(init_hw_perf_events);
* This code has been adapted from the ARM OProfile support.
*/
struct frame_tail {
struct frame_tail *fp;
unsigned long sp;
unsigned long lr;
struct frame_tail __user *fp;
unsigned long sp;
unsigned long lr;
} __attribute__((packed));
/*
* Get the return address for a single stackframe and return a pointer to the
* next frame tail.
*/
static struct frame_tail *
user_backtrace(struct frame_tail *tail,
static struct frame_tail __user *
user_backtrace(struct frame_tail __user *tail,
struct perf_callchain_entry *entry)
{
struct frame_tail buftail;
@ -709,10 +709,10 @@ user_backtrace(struct frame_tail *tail,
void
perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
{
struct frame_tail *tail;
struct frame_tail __user *tail;
tail = (struct frame_tail *)regs->ARM_fp - 1;
tail = (struct frame_tail __user *)regs->ARM_fp - 1;
while (tail && !((unsigned long)tail & 0x3))
tail = user_backtrace(tail, entry);

View File

@ -400,7 +400,7 @@ armv6pmu_write_counter(int counter,
WARN_ONCE(1, "invalid counter number (%d)\n", counter);
}
void
static void
armv6pmu_enable_event(struct hw_perf_event *hwc,
int idx)
{
@ -625,7 +625,7 @@ static const struct arm_pmu armv6pmu = {
.max_period = (1LLU << 32) - 1,
};
const struct arm_pmu *__init armv6pmu_init(void)
static const struct arm_pmu *__init armv6pmu_init(void)
{
return &armv6pmu;
}
@ -655,17 +655,17 @@ static const struct arm_pmu armv6mpcore_pmu = {
.max_period = (1LLU << 32) - 1,
};
const struct arm_pmu *__init armv6mpcore_pmu_init(void)
static const struct arm_pmu *__init armv6mpcore_pmu_init(void)
{
return &armv6mpcore_pmu;
}
#else
const struct arm_pmu *__init armv6pmu_init(void)
static const struct arm_pmu *__init armv6pmu_init(void)
{
return NULL;
}
const struct arm_pmu *__init armv6mpcore_pmu_init(void)
static const struct arm_pmu *__init armv6mpcore_pmu_init(void)
{
return NULL;
}

View File

@ -681,7 +681,7 @@ static void armv7_pmnc_dump_regs(void)
}
#endif
void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
static void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
{
unsigned long flags;
@ -874,7 +874,7 @@ static u32 __init armv7_reset_read_pmnc(void)
return nb_cnt + 1;
}
const struct arm_pmu *__init armv7_a8_pmu_init(void)
static const struct arm_pmu *__init armv7_a8_pmu_init(void)
{
armv7pmu.id = ARM_PERF_PMU_ID_CA8;
armv7pmu.name = "ARMv7 Cortex-A8";
@ -884,7 +884,7 @@ const struct arm_pmu *__init armv7_a8_pmu_init(void)
return &armv7pmu;
}
const struct arm_pmu *__init armv7_a9_pmu_init(void)
static const struct arm_pmu *__init armv7_a9_pmu_init(void)
{
armv7pmu.id = ARM_PERF_PMU_ID_CA9;
armv7pmu.name = "ARMv7 Cortex-A9";
@ -894,12 +894,12 @@ const struct arm_pmu *__init armv7_a9_pmu_init(void)
return &armv7pmu;
}
#else
const struct arm_pmu *__init armv7_a8_pmu_init(void)
static const struct arm_pmu *__init armv7_a8_pmu_init(void)
{
return NULL;
}
const struct arm_pmu *__init armv7_a9_pmu_init(void)
static const struct arm_pmu *__init armv7_a9_pmu_init(void)
{
return NULL;
}

View File

@ -428,7 +428,7 @@ static const struct arm_pmu xscale1pmu = {
.max_period = (1LLU << 32) - 1,
};
const struct arm_pmu *__init xscale1pmu_init(void)
static const struct arm_pmu *__init xscale1pmu_init(void)
{
return &xscale1pmu;
}
@ -790,17 +790,17 @@ static const struct arm_pmu xscale2pmu = {
.max_period = (1LLU << 32) - 1,
};
const struct arm_pmu *__init xscale2pmu_init(void)
static const struct arm_pmu *__init xscale2pmu_init(void)
{
return &xscale2pmu;
}
#else
const struct arm_pmu *__init xscale1pmu_init(void)
static const struct arm_pmu *__init xscale1pmu_init(void)
{
return NULL;
}
const struct arm_pmu *__init xscale2pmu_init(void)
static const struct arm_pmu *__init xscale2pmu_init(void)
{
return NULL;
}