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This pull request contains the following changes for MTD: 

MTD core changes:
 - New AFS partition parser
 - Update MAINTAINERS entry
 - Use of fall-throughs markers
 
 NAND core changes:
 - Support having the bad block markers in either the first, second or
   last page of a block. The combination of all three location is now
   possible.
 - Constification of NAND_OP_PARSER(_PATTERN) elements.
 - Generic NAND DT bindings changed to yaml format (can be used to
   check the proposed bindings. First platform to be fully supported:
   sunxi.
 - Stopped using several legacy hooks.
 - Preparation to use the generic NAND layer with the addition of
   several helpers and the removal of the struct nand_chip from generic
   functions.
 - Kconfig cleanup to prepare the introduction of external ECC engines
   support.
 - Fallthrough comments.
 - Introduction of the SPI-mem dirmap API for SPI-NAND devices.
 
 Raw NAND controller drivers changes:
 - nandsim:
   * Switch to ->exec-op().
 - meson:
   * Misc cleanups and fixes.
   * New OOB layout.
 - Sunxi:
   * A23/A33 NAND DMA support.
 - Ingenic:
   * Full reorganization and cleanup.
   * Clear separation between NAND controller and ECC engine.
   * Support JZ4740 an JZ4725B.
 - Denali:
   * Clear controller/chip separation.
   * ->exec_op() migration.
   * Various cleanups.
 - fsl_elbc:
   * Enable software ECC support.
 - Atmel:
   * Sam9x60 support.
 - GPMI:
   * Introduce the GPMI_IS_MXS() macro.
 - Various trivial/spelling/coding style fixes.
 
 SPI NOR core changes:
 - Print all JEDEC ID bytes on error
 - Fix comment of spi_nor_find_best_erase_type()
 - Add region locking flags for s25fl512s
 
 SPI NOR controller drivers changes:
 - intel-spi:
   * Avoid crossing 4K address boundary on read/write
   * Add support for Intel Comet Lake SPI serial flash
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Merge tag 'mtd/for-5.2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mtd/linux

Pull MTD updates from Richard Weinberger:
 "MTD core changes:
   - New AFS partition parser
   - Update MAINTAINERS entry
   - Use of fall-throughs markers

  NAND core changes:
   - Support having the bad block markers in either the first, second or
     last page of a block. The combination of all three location is now
     possible.
   - Constification of NAND_OP_PARSER(_PATTERN) elements.
   - Generic NAND DT bindings changed to yaml format (can be used to
     check the proposed bindings. First platform to be fully supported:
     sunxi.
   - Stopped using several legacy hooks.
   - Preparation to use the generic NAND layer with the addition of
     several helpers and the removal of the struct nand_chip from
     generic functions.
   - Kconfig cleanup to prepare the introduction of external ECC engines
     support.
   - Fallthrough comments.
   - Introduction of the SPI-mem dirmap API for SPI-NAND devices.

  Raw NAND controller drivers changes:
   - nandsim:
      - Switch to ->exec-op().
   - meson:
      - Misc cleanups and fixes.
      - New OOB layout.
   - Sunxi:
      - A23/A33 NAND DMA support.
   - Ingenic:
      - Full reorganization and cleanup.
      - Clear separation between NAND controller and ECC engine.
      - Support JZ4740 an JZ4725B.
   - Denali:
      - Clear controller/chip separation.
      - ->exec_op() migration.
      - Various cleanups.
   - fsl_elbc:
      - Enable software ECC support.
   - Atmel:
      - Sam9x60 support.
   - GPMI:
      - Introduce the GPMI_IS_MXS() macro.
   - Various trivial/spelling/coding style fixes.

  SPI NOR core changes:
   - Print all JEDEC ID bytes on error
   - Fix comment of spi_nor_find_best_erase_type()
   - Add region locking flags for s25fl512s

  SPI NOR controller drivers changes:
   - intel-spi:
      - Avoid crossing 4K address boundary on read/write
      - Add support for Intel Comet Lake SPI serial flash"

* tag 'mtd/for-5.2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (120 commits)
  mtd: part: fix incorrect format specifier for an unsigned long long
  mtd: lpddr_cmds: Mark expected switch fall-through
  mtd: phram: Mark expected switch fall-throughs
  mtd: cfi_cmdset_0002: Mark expected switch fall-throughs
  mtd: cfi_util: mark expected switch fall-throughs
  MAINTAINERS: MTD Git repository is hosted on kernel.org
  MAINTAINERS: Update jffs2 entry
  mtd: afs: add v2 partition parsing
  mtd: afs: factor the IIS read into partition parser
  mtd: afs: factor footer parsing into the v1 part parsing
  mtd: factor out v1 partition parsing
  mtd: afs: simplify partition detection
  mtd: afs: simplify partition parsing
  mtd: partitions: Add OF support to AFS partitions
  mtd: partitions: Add AFS partitions DT bindings
  mtd: afs: Move AFS partition parser to parsers subdir
  mtd: maps: Make uclinux_ram_map static
  mtd: maps: Allow MTD_PHYSMAP with MTD_RAM
  MAINTAINERS: Add myself as MTD maintainer
  MAINTAINERS: Remove my name from the MTD and NAND entries
  ...
hifive-unleashed-5.2
Linus Torvalds 2019-05-12 17:57:52 -04:00
parent 983dfa4b6e 3008ba8709
commit 4dbf09fea6
187 changed files with 4976 additions and 3075 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt
View File

@ -15,6 +15,7 @@ Required properties:
"atmel,at91sam9g45-ebi"
"atmel,at91sam9x5-ebi"
"atmel,sama5d3-ebi"
"microchip,sam9x60-ebi"
- reg: Contains offset/length value for EBI memory mapping.
This property might contain several entries if the EBI

97
Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml 100644
View File

@ -0,0 +1,97 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 NAND Controller Device Tree Bindings
allOf:
- $ref: "nand-controller.yaml"
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <maxime.ripard@bootlin.com>
properties:
"#address-cells": true
"#size-cells": true
compatible:
enum:
- allwinner,sun4i-a10-nand
- allwinner,sun8i-a23-nand-controller
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: Bus Clock
- description: Module Clock
clock-names:
items:
- const: ahb
- const: mod
resets:
maxItems: 1
reset-names:
const: ahb
dmas:
maxItems: 1
dma-names:
const: rxtx
pinctrl-names: true
patternProperties:
"^pinctrl-[0-9]+$": true
"^nand@[a-f0-9]+$":
properties:
reg:
maxItems: 1
minimum: 0
maximum: 7
nand-ecc-mode: true
nand-ecc-algo:
const: bch
nand-ecc-step-size:
enum: [ 512, 1024 ]
nand-ecc-strength:
maximum: 80
allwinner,rb:
description:
Contains the native Ready/Busy IDs.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- minItems: 1
maxItems: 2
items:
minimum: 0
maximum: 1
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
...

1
Documentation/devicetree/bindings/mtd/atmel-nand.txt
View File

@ -14,6 +14,7 @@ Required properties:
"atmel,at91sam9261-nand-controller"
"atmel,at91sam9g45-nand-controller"
"atmel,sama5d3-nand-controller"
"microchip,sam9x60-nand-controller"
- ranges: empty ranges property to forward EBI ranges definitions.
- #address-cells: should be set to 2.
- #size-cells: should be set to 1.

38
Documentation/devicetree/bindings/mtd/denali-nand.txt
View File

@ -7,34 +7,48 @@ Required properties:
"socionext,uniphier-denali-nand-v5b" - for Socionext UniPhier (v5b)
- reg : should contain registers location and length for data and reg.
- reg-names: Should contain the reg names "nand_data" and "denali_reg"
- #address-cells: should be 1. The cell encodes the chip select connection.
- #size-cells : should be 0.
- interrupts : The interrupt number.
- clocks: should contain phandle of the controller core clock, the bus
interface clock, and the ECC circuit clock.
- clock-names: should contain "nand", "nand_x", "ecc"
Optional properties:
- nand-ecc-step-size: see nand.txt for details. If present, the value must be
512 for "altr,socfpga-denali-nand"
1024 for "socionext,uniphier-denali-nand-v5a"
1024 for "socionext,uniphier-denali-nand-v5b"
- nand-ecc-strength: see nand.txt for details. Valid values are:
8, 15 for "altr,socfpga-denali-nand"
8, 16, 24 for "socionext,uniphier-denali-nand-v5a"
8, 16 for "socionext,uniphier-denali-nand-v5b"
- nand-ecc-maximize: see nand.txt for details
Sub-nodes:
Sub-nodes represent available NAND chips.
The device tree may optionally contain sub-nodes describing partitions of the
Required properties:
- reg: should contain the bank ID of the controller to which each chip
select is connected.
Optional properties:
- nand-ecc-step-size: see nand.txt for details.
If present, the value must be
512 for "altr,socfpga-denali-nand"
1024 for "socionext,uniphier-denali-nand-v5a"
1024 for "socionext,uniphier-denali-nand-v5b"
- nand-ecc-strength: see nand.txt for details. Valid values are:
8, 15 for "altr,socfpga-denali-nand"
8, 16, 24 for "socionext,uniphier-denali-nand-v5a"
8, 16 for "socionext,uniphier-denali-nand-v5b"
- nand-ecc-maximize: see nand.txt for details
The chip nodes may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail.
Examples:
nand: nand@ff900000 {
#address-cells = <1>;
#size-cells = <1>;
#size-cells = <0>;
compatible = "altr,socfpga-denali-nand";
reg = <0xff900000 0x20>, <0xffb80000 0x1000>;
reg-names = "nand_data", "denali_reg";
clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
clock-names = "nand", "nand_x", "ecc";
interrupts = <0 144 4>;
nand@0 {
reg = <0>;
}
};

30
Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
View File

@ -1,4 +1,4 @@
* Ingenic JZ4780 NAND/BCH
* Ingenic JZ4780 NAND/ECC
This file documents the device tree bindings for NAND flash devices on the
JZ4780. NAND devices are connected to the NEMC controller (described in
@ -6,15 +6,18 @@ memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must
be children of the NEMC node.
Required NAND controller device properties:
- compatible: Should be set to "ingenic,jz4780-nand".
- compatible: Should be one of:
* ingenic,jz4740-nand
* ingenic,jz4725b-nand
* ingenic,jz4780-nand
- reg: For each bank with a NAND chip attached, should specify a bank number,
an offset of 0 and a size of 0x1000000 (i.e. the whole NEMC bank).
Optional NAND controller device properties:
- ingenic,bch-controller: To make use of the hardware BCH controller, this
property must contain a phandle for the BCH controller node. The required
- ecc-engine: To make use of the hardware ECC controller, this
property must contain a phandle for the ECC controller node. The required
properties for this node are described below. If this is not specified,
software BCH will be used instead.
software ECC will be used instead.
Optional children nodes:
- Individual NAND chips are children of the NAND controller node.
@ -45,7 +48,7 @@ nemc: nemc@13410000 {
#address-cells = <1>;
#size-cells = <0>;
ingenic,bch-controller = <&bch>;
ecc-engine = <&bch>;
nand@1 {
reg = <1>;
@ -67,14 +70,17 @@ nemc: nemc@13410000 {
};
};
The BCH controller is a separate SoC component used for error correction on
The ECC controller is a separate SoC component used for error correction on
NAND devices. The following is a description of the device properties for a
BCH controller.
ECC controller.
Required BCH properties:
- compatible: Should be set to "ingenic,jz4780-bch".
- reg: Should specify the BCH controller registers location and length.
- clocks: Clock for the BCH controller.
Required ECC properties:
- compatible: Should be one of:
* ingenic,jz4740-ecc
* ingenic,jz4725b-bch
* ingenic,jz4780-bch
- reg: Should specify the ECC controller registers location and length.
- clocks: Clock for the ECC controller.
Example:

16
Documentation/devicetree/bindings/mtd/mtd-physmap.txt
View File

@ -96,3 +96,19 @@ An example using SRAM:
bank-width = <2>;
};
An example using gpio-addrs
flash@20000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash", "jedec-flash";
reg = <0x20000000 0x02000000>;
ranges = <0 0x00000000 0x02000000
1 0x02000000 0x02000000>;
bank-width = <2>;
addr-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
partition@0 {
label = "test-part1";
reg = <0 0x04000000>;
};
};

143
Documentation/devicetree/bindings/mtd/nand-controller.yaml 100644
View File

@ -0,0 +1,143 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NAND Chip and NAND Controller Generic Binding
maintainers:
- Miquel Raynal <miquel.raynal@bootlin.com>
- Richard Weinberger <richard@nod.at>
description: |
The NAND controller should be represented with its own DT node, and
all NAND chips attached to this controller should be defined as
children nodes of the NAND controller. This representation should be
enforced even for simple controllers supporting only one chip.
The ECC strength and ECC step size properties define the user
desires in terms of correction capability of a controller. Together,
they request the ECC engine to correct {strength} bit errors per
{size} bytes.
The interpretation of these parameters is implementation-defined, so
not all implementations must support all possible
combinations. However, implementations are encouraged to further
specify the value(s) they support.
properties:
$nodename:
pattern: "^nand-controller(@.*)?"
"#address-cells":
const: 1
"#size-cells":
const: 0
ranges: true
patternProperties:
"^nand@[a-f0-9]$":
properties:
reg:
description:
Contains the native Ready/Busy IDs.
nand-ecc-mode:
allOf:
- $ref: /schemas/types.yaml#/definitions/string
- enum: [ none, soft, hw, hw_syndrome, hw_oob_first, on-die ]
description:
Desired ECC engine, either hardware (most of the time
embedded in the NAND controller) or software correction
(Linux will handle the calculations). soft_bch is deprecated
and should be replaced by soft and nand-ecc-algo.
nand-ecc-algo:
allOf:
- $ref: /schemas/types.yaml#/definitions/string
- enum: [ hamming, bch, rs ]
description:
Desired ECC algorithm.
nand-bus-width:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 8, 16 ]
- default: 8
description:
Bus width to the NAND chip
nand-on-flash-bbt:
$ref: /schemas/types.yaml#/definitions/flag
description:
With this property, the OS will search the device for a Bad
Block Table (BBT). If not found, it will create one, reserve
a few blocks at the end of the device to store it and update
it as the device ages. Otherwise, the out-of-band area of a
few pages of all the blocks will be scanned at boot time to
find Bad Block Markers (BBM). These markers will help to
build a volatile BBT in RAM.
nand-ecc-strength:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 1
description:
Maximum number of bits that can be corrected per ECC step.
nand-ecc-step-size:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 1
description:
Number of data bytes covered by a single ECC step.
nand-ecc-maximize:
$ref: /schemas/types.yaml#/definitions/flag
description:
Whether or not the ECC strength should be maximized. The
maximum ECC strength is both controller and chip
dependent. The ECC engine has to select the ECC config
providing the best strength and taking the OOB area size
constraint into account. This is particularly useful when
only the in-band area is used by the upper layers, and you
want to make your NAND as reliable as possible.
nand-is-boot-medium:
$ref: /schemas/types.yaml#/definitions/flag
description:
Whether or not the NAND chip is a boot medium. Drivers might
use this information to select ECC algorithms supported by
the boot ROM or similar restrictions.
nand-rb:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
Contains the native Ready/Busy IDs.
required:
- reg
required:
- "#address-cells"
- "#size-cells"
examples:
- |
nand-controller {
#address-cells = <1>;
#size-cells = <0>;
/* controller specific properties */
nand@0 {
reg = <0>;
nand-ecc-mode = "soft";
nand-ecc-algo = "bch";
/* controller specific properties */
};
};

75
Documentation/devicetree/bindings/mtd/nand.txt
View File

@ -1,75 +0,0 @@
* NAND chip and NAND controller generic binding
NAND controller/NAND chip representation:
The NAND controller should be represented with its own DT node, and all
NAND chips attached to this controller should be defined as children nodes
of the NAND controller. This representation should be enforced even for
simple controllers supporting only one chip.
Mandatory NAND controller properties:
- #address-cells: depends on your controller. Should at least be 1 to
encode the CS line id.
- #size-cells: depends on your controller. Put zero unless you need a
mapping between CS lines and dedicated memory regions
Optional NAND controller properties
- ranges: only needed if you need to define a mapping between CS lines and
memory regions
Optional NAND chip properties:
- nand-ecc-mode : String, operation mode of the NAND ecc mode.
Supported values are: "none", "soft", "hw", "hw_syndrome",
"hw_oob_first", "on-die".
Deprecated values:
"soft_bch": use "soft" and nand-ecc-algo instead
- nand-ecc-algo: string, algorithm of NAND ECC.
Valid values are: "hamming", "bch", "rs".
- nand-bus-width : 8 or 16 bus width if not present 8
- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
- nand-ecc-strength: integer representing the number of bits to correct
per ECC step.
- nand-ecc-step-size: integer representing the number of data bytes
that are covered by a single ECC step.
- nand-ecc-maximize: boolean used to specify that you want to maximize ECC
strength. The maximum ECC strength is both controller and
chip dependent. The controller side has to select the ECC
config providing the best strength and taking the OOB area
size constraint into account.
This is particularly useful when only the in-band area is
used by the upper layers, and you want to make your NAND
as reliable as possible.
- nand-is-boot-medium: Whether the NAND chip is a boot medium. Drivers might use
this information to select ECC algorithms supported by
the boot ROM or similar restrictions.
- nand-rb: shall contain the native Ready/Busy ids.
The ECC strength and ECC step size properties define the correction capability
of a controller. Together, they say a controller can correct "{strength} bit
errors per {size} bytes".
The interpretation of these parameters is implementation-defined, so not all
implementations must support all possible combinations. However, implementations
are encouraged to further specify the value(s) they support.
Example:
nand-controller {
#address-cells = <1>;
#size-cells = <0>;
/* controller specific properties */
nand@0 {
reg = <0>;
nand-ecc-mode = "soft";
nand-ecc-algo = "bch";
/* controller specific properties */
};
};

17
Documentation/devicetree/bindings/mtd/partitions/arm,arm-firmware-suite.txt 100644
View File

@ -0,0 +1,17 @@
ARM AFS - ARM Firmware Suite Partitions
=======================================
The ARM Firmware Suite is a flash partitioning system found on the
ARM reference designs: Integrator AP, Integrator CP, Versatile AB,
Versatile PB, the RealView family, Versatile Express and Juno.
Required properties:
- compatible : (required) must be "arm,arm-firmware-suite"
Example:
flash@0 {
partitions {
compatible = "arm,arm-firmware-suite";
};
};

24
Documentation/devicetree/bindings/mtd/partitions/brcm,bcm963xx-cfe-nor-partitions.txt 100644
View File

@ -0,0 +1,24 @@
Broadcom BCM963XX CFE Loader NOR Flash Partitions
=================================================
Most Broadcom BCM63XX SoC based devices follow the Broadcom reference layout for
NOR. The first erase block used for the CFE bootloader, the last for an
NVRAM partition, and the remainder in-between for one to two firmware partitions
at fixed offsets. A valid firmware partition is identified by the ImageTag
header found at beginning of the second erase block, containing the rootfs and
kernel offsets and sizes within the firmware partition.
Required properties:
- compatible : must be "brcm,bcm963xx-cfe-nor-partitions"
Example:
flash@1fc00000 {
compatible = "cfi-flash";
reg = <0x1fc00000 0x400000>;
bank-width = <2>;
partitions {
compatible = "brcm,bcm963xx-cfe-nor-partitions";
};
};

45
Documentation/devicetree/bindings/mtd/partitions/brcm,bcm963xx-imagetag.txt 100644
View File

@ -0,0 +1,45 @@
Broadcom BCM963XX ImageTag Partition Container
==============================================
Some Broadcom BCM63XX SoC based devices contain additional, non discoverable
partitions or non standard bootloader partition sizes. For these a mixed layout
needs to be used with an explicit firmware partition.
The BCM963XX ImageTag is a simple firmware header describing the offsets and
sizes of the rootfs and kernel parts contained in the firmware.
Required properties:
- compatible : must be "brcm,bcm963xx-imagetag"
Example:
flash@1e000000 {
compatible = "cfi-flash";
reg = <0x1e000000 0x2000000>;
bank-width = <2>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
cfe@0 {
reg = <0x0 0x10000>;
read-only;
};
firmware@10000 {
reg = <0x10000 0x7d0000>;
compatible = "brcm,bcm963xx-imagetag";
};
caldata@7e0000 {
reg = <0x7e0000 0x10000>;
read-only;
};
nvram@7f0000 {
reg = <0x7f0000 0x10000>;
};
};
};

48
Documentation/devicetree/bindings/mtd/sunxi-nand.txt
View File

@ -1,48 +0,0 @@
Allwinner NAND Flash Controller (NFC)
Required properties:
- compatible : "allwinner,sun4i-a10-nand".
- reg : shall contain registers location and length for data and reg.
- interrupts : shall define the nand controller interrupt.
- #address-cells: shall be set to 1. Encode the nand CS.
- #size-cells : shall be set to 0.
- clocks : shall reference nand controller clocks.
- clock-names : nand controller internal clock names. Shall contain :
* "ahb" : AHB gating clock
* "mod" : nand controller clock
Optional properties:
- dmas : shall reference DMA channel associated to the NAND controller.
- dma-names : shall be "rxtx".
Optional children nodes:
Children nodes represent the available nand chips.
Optional properties:
- reset : phandle + reset specifier pair
- reset-names : must contain "ahb"
- allwinner,rb : shall contain the native Ready/Busy ids.
- nand-ecc-mode : one of the supported ECC modes ("hw", "soft", "soft_bch" or
"none")
see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
Examples:
nfc: nand@1c03000 {
compatible = "allwinner,sun4i-a10-nand";
reg = <0x01c03000 0x1000>;
interrupts = <0 37 1>;
clocks = <&ahb_gates 13>, <&nand_clk>;
clock-names = "ahb", "mod";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
nand@0 {
reg = <0>;
allwinner,rb = <0>;
nand-ecc-mode = "soft_bch";
};
};

18
MAINTAINERS
View File

@ -8418,9 +8418,11 @@ F: drivers/net/ethernet/jme.*
JOURNALLING FLASH FILE SYSTEM V2 (JFFS2)
M: David Woodhouse <dwmw2@infradead.org>
M: Richard Weinberger <richard@nod.at>
L: linux-mtd@lists.infradead.org
W: http://www.linux-mtd.infradead.org/doc/jffs2.html
S: Maintained
T: git git://git.infradead.org/ubifs-2.6.git
S: Odd Fixes
F: fs/jffs2/
F: include/uapi/linux/jffs2.h
@ -10114,14 +10116,15 @@ F: mm/
MEMORY TECHNOLOGY DEVICES (MTD)
M: David Woodhouse <dwmw2@infradead.org>
M: Brian Norris <computersforpeace@gmail.com>
M: Boris Brezillon <bbrezillon@kernel.org>
M: Marek Vasut <marek.vasut@gmail.com>
M: Miquel Raynal <miquel.raynal@bootlin.com>
M: Richard Weinberger <richard@nod.at>
M: Vignesh Raghavendra <vigneshr@ti.com>
L: linux-mtd@lists.infradead.org
W: http://www.linux-mtd.infradead.org/
Q: http://patchwork.ozlabs.org/project/linux-mtd/list/
T: git git://git.infradead.org/linux-mtd.git master
T: git git://git.infradead.org/linux-mtd.git mtd/next
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git mtd/fixes
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git mtd/next
S: Maintained
F: Documentation/devicetree/bindings/mtd/
F: drivers/mtd/
@ -10730,14 +10733,12 @@ S: Supported
F: drivers/net/ethernet/myricom/myri10ge/
NAND FLASH SUBSYSTEM
M: Boris Brezillon <bbrezillon@kernel.org>
M: Miquel Raynal <miquel.raynal@bootlin.com>
R: Richard Weinberger <richard@nod.at>
L: linux-mtd@lists.infradead.org
W: http://www.linux-mtd.infradead.org/
Q: http://patchwork.ozlabs.org/project/linux-mtd/list/
T: git git://git.infradead.org/linux-mtd.git nand/fixes
T: git git://git.infradead.org/linux-mtd.git nand/next
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next
S: Maintained
F: drivers/mtd/nand/
F: include/linux/mtd/*nand*.h
@ -14751,8 +14752,7 @@ M: Tudor Ambarus <tudor.ambarus@microchip.com>
L: linux-mtd@lists.infradead.org
W: http://www.linux-mtd.infradead.org/
Q: http://patchwork.ozlabs.org/project/linux-mtd/list/
T: git git://git.infradead.org/linux-mtd.git spi-nor/fixes
T: git git://git.infradead.org/linux-mtd.git spi-nor/next
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git spi-nor/next
S: Maintained
F: drivers/mtd/spi-nor/
F: include/linux/mtd/spi-nor.h

2
arch/arm/configs/at91_dt_defconfig
View File

@ -55,7 +55,7 @@ CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_GLUEBI=y

2
arch/arm/configs/clps711x_defconfig
View File

@ -35,7 +35,7 @@ CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PLATRAM=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_GPIO=y
CONFIG_NETDEVICES=y
# CONFIG_NET_CADENCE is not set

2
arch/arm/configs/cm_x2xx_defconfig
View File

@ -58,7 +58,7 @@ CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PXA2XX=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_GPIO=m
CONFIG_MTD_NAND_CM_X270=y
CONFIG_MTD_NAND_PLATFORM=y

2
arch/arm/configs/cm_x300_defconfig
View File

@ -48,7 +48,7 @@ CONFIG_LIB80211=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y

2
arch/arm/configs/colibri_pxa270_defconfig
View File

@ -64,7 +64,7 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PXA2XX=y
CONFIG_MTD_BLOCK2MTD=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_DISKONCHIP=y
CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000

2
arch/arm/configs/corgi_defconfig
View File

@ -87,7 +87,7 @@ CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_ROM=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_SHARPSL=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_SD=y

2
arch/arm/configs/davinci_all_defconfig
View File

@ -74,7 +74,7 @@ CONFIG_MTD_CFI_INTELEXT=m
CONFIG_MTD_CFI_AMDSTD=m
CONFIG_MTD_PHYSMAP=m
CONFIG_MTD_M25P80=m
CONFIG_MTD_NAND=m
CONFIG_MTD_RAW_NAND=m
CONFIG_MTD_NAND_DAVINCI=m
CONFIG_MTD_SPI_NOR=m
CONFIG_MTD_UBI=m

2
arch/arm/configs/em_x270_defconfig
View File

@ -54,7 +54,7 @@ CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PXA2XX=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y

2
arch/arm/configs/ep93xx_defconfig
View File

@ -63,7 +63,7 @@ CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_ROM=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_BLK_DEV_NBD=y
CONFIG_EEPROM_LEGACY=y
CONFIG_SCSI=y

2
arch/arm/configs/eseries_pxa_defconfig
View File

@ -43,7 +43,7 @@ CONFIG_MAC80211_RC_PID=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_STANDALONE is not set
CONFIG_MTD=m
CONFIG_MTD_NAND=m
CONFIG_MTD_RAW_NAND=m
CONFIG_MTD_NAND_TMIO=m
CONFIG_BLK_DEV_LOOP=m
# CONFIG_SCSI_PROC_FS is not set

2
arch/arm/configs/imx_v4_v5_defconfig
View File

@ -61,7 +61,7 @@ CONFIG_MTD_CFI_GEOMETRY=y
# CONFIG_MTD_CFI_I2 is not set
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_MXC=y
CONFIG_MTD_UBI=y
CONFIG_EEPROM_AT24=y

2
arch/arm/configs/imx_v6_v7_defconfig
View File

@ -110,7 +110,7 @@ CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_SST25L=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_GPMI_NAND=y
CONFIG_MTD_NAND_VF610_NFC=y
CONFIG_MTD_NAND_MXC=y

2
arch/arm/configs/ixp4xx_defconfig
View File

@ -112,7 +112,7 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_IXP4XX=y
CONFIG_MTD_NAND=m
CONFIG_MTD_RAW_NAND=m
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192

2
arch/arm/configs/keystone_defconfig
View File

@ -124,7 +124,7 @@ CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_PLATRAM=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_DAVINCI=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y

2
arch/arm/configs/lpc32xx_defconfig
View File

@ -47,7 +47,7 @@ CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_SLC_LPC32XX=y
CONFIG_MTD_NAND_MLC_LPC32XX=y
CONFIG_MTD_UBI=y

2
arch/arm/configs/mini2440_defconfig
View File

@ -92,7 +92,7 @@ CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_RAM=y
CONFIG_MTD_ROM=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_S3C2410=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_LPDDR=y

2
arch/arm/configs/mmp2_defconfig
View File

@ -28,7 +28,7 @@ CONFIG_IP_PNP=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_ONENAND=y
CONFIG_MTD_ONENAND_GENERIC=y
# CONFIG_BLK_DEV is not set

2
arch/arm/configs/multi_v4t_defconfig
View File

@ -38,7 +38,7 @@ CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PLATRAM=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_GPIO=y
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set

2
arch/arm/configs/multi_v5_defconfig
View File

@ -87,7 +87,7 @@ CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_NAND_ORION=y
CONFIG_MTD_SPI_NOR=y

2
arch/arm/configs/multi_v7_defconfig
View File

@ -184,7 +184,7 @@ CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_DENALI_DT=y
CONFIG_MTD_NAND_OMAP2=y
CONFIG_MTD_NAND_OMAP_BCH=y

2
arch/arm/configs/mv78xx0_defconfig
View File

@ -47,7 +47,7 @@ CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_ORION=y
CONFIG_BLK_DEV_LOOP=y
# CONFIG_SCSI_PROC_FS is not set

2
arch/arm/configs/mvebu_v5_defconfig
View File

@ -77,7 +77,7 @@ CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_ORION=y
CONFIG_MTD_SPI_NOR=y
CONFIG_BLK_DEV_LOOP=y

2
arch/arm/configs/mvebu_v7_defconfig
View File

@ -52,7 +52,7 @@ CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y

2
arch/arm/configs/mxs_defconfig
View File

@ -50,7 +50,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_SST25L=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_GPMI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y

4
arch/arm/configs/nhk8815_defconfig
View File

@ -53,8 +53,8 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_ONENAND=y
CONFIG_MTD_ONENAND_VERIFY_WRITE=y
CONFIG_MTD_ONENAND_GENERIC=y
CONFIG_MTD_NAND_ECC_SMC=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_FSMC=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_CRYPTOLOOP=y

2
arch/arm/configs/omap1_defconfig
View File

@ -89,7 +89,7 @@ CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=2

4
arch/arm/configs/omap2plus_defconfig
View File

@ -143,8 +143,8 @@ CONFIG_MTD_M25P80=m
CONFIG_MTD_ONENAND=y
CONFIG_MTD_ONENAND_VERIFY_WRITE=y
CONFIG_MTD_ONENAND_OMAP2=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ECC_BCH=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_ECC_SW_BCH=y
CONFIG_MTD_NAND_OMAP2=y
CONFIG_MTD_NAND_OMAP_BCH=y
CONFIG_MTD_SPI_NOR=m

2
arch/arm/configs/orion5x_defconfig
View File

@ -70,7 +70,7 @@ CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_NAND_ORION=y
CONFIG_BLK_DEV_LOOP=y

2
arch/arm/configs/oxnas_v6_defconfig
View File

@ -50,7 +50,7 @@ CONFIG_SIMPLE_PM_BUS=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_OXNAS=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y

2
arch/arm/configs/pxa3xx_defconfig
View File

@ -31,7 +31,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_ONENAND=y
CONFIG_MTD_ONENAND_VERIFY_WRITE=y

4
arch/arm/configs/pxa_defconfig
View File

@ -185,8 +185,8 @@ CONFIG_MTD_PXA2XX=m
CONFIG_MTD_M25P80=m
CONFIG_MTD_BLOCK2MTD=y
CONFIG_MTD_DOCG3=m
CONFIG_MTD_NAND=m
CONFIG_MTD_NAND_ECC_BCH=y
CONFIG_MTD_RAW_NAND=m
CONFIG_MTD_NAND_ECC_SW_BCH=y
CONFIG_MTD_NAND_GPIO=m
CONFIG_MTD_NAND_DISKONCHIP=m
CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y

2
arch/arm/configs/qcom_defconfig
View File

@ -57,7 +57,7 @@ CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_QCOM=y
CONFIG_MTD_SPI_NOR=y
CONFIG_BLK_DEV_LOOP=y

2
arch/arm/configs/s3c2410_defconfig
View File

@ -192,7 +192,7 @@ CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_ROM=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_S3C2410=y
CONFIG_PARPORT=y
CONFIG_PARPORT_PC=m

2
arch/arm/configs/s3c6400_defconfig
View File

@ -23,7 +23,7 @@ CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/linuxrc initrd=0x5100
CONFIG_VFP=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_S3C2410=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y

2
arch/arm/configs/sama5_defconfig
View File

@ -66,7 +66,7 @@ CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y

2
arch/arm/configs/socfpga_defconfig
View File

@ -51,7 +51,7 @@ CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_DENALI_DT=y
CONFIG_MTD_SPI_NOR=y
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set

2
arch/arm/configs/spear13xx_defconfig
View File

@ -32,7 +32,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_FSMC=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384

2
arch/arm/configs/spear3xx_defconfig
View File

@ -17,7 +17,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_FSMC=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384

2
arch/arm/configs/spear6xx_defconfig
View File

@ -14,7 +14,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_FSMC=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384

2
arch/arm/configs/spitz_defconfig
View File

@ -84,7 +84,7 @@ CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_ROM=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_SHARPSL=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_SD=y

2
arch/arm/configs/tango4_defconfig
View File

@ -39,7 +39,7 @@ CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_TESTS=m
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_TANGO=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_SCSI=y

2
arch/arm/configs/trizeps4_defconfig
View File

@ -76,7 +76,7 @@ CONFIG_MTD_DOC2001PLUS=y
CONFIG_MTD_DOCPROBE_ADVANCED=y
CONFIG_MTD_DOCPROBE_ADDRESS=0x4000000
CONFIG_MTD_DOCPROBE_HIGH=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_DISKONCHIP=y
CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000

2
arch/arm/configs/u300_defconfig
View File

@ -26,7 +26,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_FSMC=y
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y

2
arch/arm64/configs/defconfig
View File

@ -206,7 +206,7 @@ CONFIG_SIMPLE_PM_BUS=y
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_DENALI_DT=y
CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_NAND_QCOM=y

2
arch/mips/configs/bcm47xx_defconfig
View File

@ -41,7 +41,7 @@ CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_BCM47XXSFLASH=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_BCM47XXNFLASH=y
CONFIG_NETDEVICES=y
CONFIG_B44=y

2
arch/mips/configs/ci20_defconfig
View File

@ -51,7 +51,7 @@ CONFIG_DEVTMPFS=y
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=32
CONFIG_MTD=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_JZ4780=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_FASTMAP=y

4
arch/mips/configs/db1xxx_defconfig
View File

@ -95,8 +95,8 @@ CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_SST25L=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ECC_BCH=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_ECC_SW_BCH=y
CONFIG_MTD_NAND_AU1550=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_SPI_NOR=y

6
arch/mips/configs/generic/board-ni169445.config
View File

@ -15,9 +15,9 @@ CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_BCH=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_ECC_SW_BCH=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_GPIO=y
CONFIG_MTD_NAND_IDS=y

2
arch/mips/configs/generic/board-ocelot.config
View File

@ -10,7 +10,7 @@ CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y

2
arch/mips/configs/loongson1b_defconfig
View File

@ -41,7 +41,7 @@ CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_SCSI=m

2
arch/mips/configs/loongson1c_defconfig
View File

@ -42,7 +42,7 @@ CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_SCSI=m

2
arch/mips/configs/qi_lb60_defconfig
View File

@ -44,7 +44,7 @@ CONFIG_TCP_CONG_WESTWOOD=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_JZ4740=y
CONFIG_MTD_UBI=y
CONFIG_NETDEVICES=y

2
arch/mips/configs/rb532_defconfig
View File

@ -109,7 +109,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_BLOCK2MTD=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_ATA=y
# CONFIG_ATA_VERBOSE_ERROR is not set

2
arch/mips/configs/rbtx49xx_defconfig
View File

@ -39,7 +39,7 @@ CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_RBTX4939=y
CONFIG_MTD_NAND=m
CONFIG_MTD_RAW_NAND=m
CONFIG_MTD_NAND_TXX9NDFMC=m
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y

2
arch/mips/configs/xway_defconfig
View File

@ -81,7 +81,7 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_LANTIQ=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_XWAY=y
CONFIG_EEPROM_93CX6=m
CONFIG_SCSI=y

2
arch/powerpc/configs/40x/kilauea_defconfig
View File

@ -33,7 +33,7 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_NDFC=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000

2
arch/powerpc/configs/40x/obs600_defconfig
View File

@ -33,7 +33,7 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_NDFC=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000

2
arch/powerpc/configs/44x/canyonlands_defconfig
View File

@ -32,7 +32,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_NDFC=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000

2
arch/powerpc/configs/44x/eiger_defconfig
View File

@ -33,7 +33,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_NDFC=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000

2
arch/powerpc/configs/44x/sequoia_defconfig
View File

@ -33,7 +33,7 @@ CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_NDFC=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000

2
arch/powerpc/configs/44x/warp_defconfig
View File

@ -34,7 +34,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_NDFC=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_RAM=y

2
arch/powerpc/configs/83xx/mpc8313_rdb_defconfig
View File

@ -31,7 +31,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_FSL_ELBC=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y

2
arch/powerpc/configs/83xx/mpc8315_rdb_defconfig
View File

@ -31,7 +31,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=32768

2
arch/powerpc/configs/85xx-hw.config
View File

@ -71,7 +71,7 @@ CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND_FSL_ELBC=y
CONFIG_MTD_NAND_FSL_IFC=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PLATRAM=y

2
arch/powerpc/configs/85xx/ge_imp3a_defconfig
View File

@ -73,7 +73,7 @@ CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_FSL_ELBC=y
CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_CRYPTOLOOP=m

2
arch/powerpc/configs/85xx/socrates_defconfig
View File

@ -31,7 +31,7 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_SOCRATES=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y

4
arch/powerpc/configs/85xx/tqm8548_defconfig
View File

@ -35,8 +35,8 @@ CONFIG_MTD=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND_ECC_SMC=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_FSL_UPM=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y

2
arch/powerpc/configs/85xx/xes_mpc85xx_defconfig
View File

@ -65,7 +65,7 @@ CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_FSL_ELBC=y
CONFIG_MTD_NAND_FSL_UPM=y
CONFIG_BLK_DEV_LOOP=y

2
arch/powerpc/configs/86xx-hw.config
View File

@ -47,7 +47,7 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_NAND_FSL_ELBC=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_NETDEVICES=y
CONFIG_NET_TULIP=y

2
arch/powerpc/configs/mpc512x_defconfig
View File

@ -46,7 +46,7 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_ROM=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_MPC5121_NFC=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_RAM=y

2
arch/powerpc/configs/mpc83xx_defconfig
View File

@ -46,7 +46,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_FSL_ELBC=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y

2
arch/powerpc/configs/pasemi_defconfig
View File

@ -51,7 +51,7 @@ CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_SLRAM=y
CONFIG_MTD_PHRAM=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_PASEMI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y

2
arch/powerpc/configs/ppc44x_defconfig
View File

@ -44,7 +44,7 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=m
CONFIG_MTD_RAW_NAND=m
CONFIG_MTD_NAND_NDFC=m
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_GLUEBI=m

2
arch/sh/configs/ap325rxa_defconfig
View File

@ -35,7 +35,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_SH_FLCTL=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_RAM=y

2
arch/sh/configs/ecovec24_defconfig
View File

@ -38,7 +38,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=4

2
arch/sh/configs/migor_defconfig
View File

@ -34,7 +34,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_BLK_DEV_RAM=y
CONFIG_SCSI=y

2
arch/sh/configs/sdk7786_defconfig
View File

@ -108,7 +108,7 @@ CONFIG_MTD_ROM=m
CONFIG_MTD_ABSENT=m
CONFIG_MTD_PLATRAM=y
CONFIG_MTD_PHRAM=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_NAND_SH_FLCTL=m
CONFIG_MTD_UBI=y

2
arch/sh/configs/se7724_defconfig
View File

@ -37,7 +37,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=4

2
arch/sh/configs/titan_defconfig
View File

@ -155,7 +155,7 @@ CONFIG_INFTL=m
CONFIG_RFD_FTL=m
CONFIG_MTD_CFI=m
CONFIG_MTD_JEDECPROBE=m
CONFIG_MTD_NAND=m
CONFIG_MTD_RAW_NAND=m
CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_CRYPTOLOOP=m
CONFIG_BLK_DEV_RAM=y

37
drivers/memory/atmel-ebi.c
View File

@ -17,6 +17,7 @@
#include <linux/init.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <soc/at91/atmel-sfr.h>
struct atmel_ebi_dev_config {
int cs;
@ -36,6 +37,7 @@ struct atmel_ebi_dev {
struct atmel_ebi_caps {
unsigned int available_cs;
unsigned int ebi_csa_offs;
const char *regmap_name;
void (*get_config)(struct atmel_ebi_dev *ebid,
struct atmel_ebi_dev_config *conf);
int (*xlate_config)(struct atmel_ebi_dev *ebid,
@ -47,7 +49,7 @@ struct atmel_ebi_caps {
struct atmel_ebi {
struct clk *clk;
struct regmap *matrix;
struct regmap *regmap;
struct {
struct regmap *regmap;
struct clk *clk;
@ -357,7 +359,7 @@ static int atmel_ebi_dev_setup(struct atmel_ebi *ebi, struct device_node *np,
* one "atmel,smc-" property is present.
*/
if (ebi->caps->ebi_csa_offs && apply)
regmap_update_bits(ebi->matrix,
regmap_update_bits(ebi->regmap,
ebi->caps->ebi_csa_offs,
BIT(cs), 0);
@ -372,6 +374,7 @@ static int atmel_ebi_dev_setup(struct atmel_ebi *ebi, struct device_node *np,
static const struct atmel_ebi_caps at91sam9260_ebi_caps = {
.available_cs = 0xff,
.ebi_csa_offs = AT91SAM9260_MATRIX_EBICSA,
.regmap_name = "atmel,matrix",
.get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config,
@ -380,6 +383,7 @@ static const struct atmel_ebi_caps at91sam9260_ebi_caps = {
static const struct atmel_ebi_caps at91sam9261_ebi_caps = {
.available_cs = 0xff,
.ebi_csa_offs = AT91SAM9261_MATRIX_EBICSA,
.regmap_name = "atmel,matrix",
.get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config,
@ -388,6 +392,7 @@ static const struct atmel_ebi_caps at91sam9261_ebi_caps = {
static const struct atmel_ebi_caps at91sam9263_ebi0_caps = {
.available_cs = 0x3f,
.ebi_csa_offs = AT91SAM9263_MATRIX_EBI0CSA,
.regmap_name = "atmel,matrix",
.get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config,
@ -396,6 +401,7 @@ static const struct atmel_ebi_caps at91sam9263_ebi0_caps = {
static const struct atmel_ebi_caps at91sam9263_ebi1_caps = {
.available_cs = 0x7,
.ebi_csa_offs = AT91SAM9263_MATRIX_EBI1CSA,
.regmap_name = "atmel,matrix",
.get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config,
@ -404,6 +410,7 @@ static const struct atmel_ebi_caps at91sam9263_ebi1_caps = {
static const struct atmel_ebi_caps at91sam9rl_ebi_caps = {
.available_cs = 0x3f,
.ebi_csa_offs = AT91SAM9RL_MATRIX_EBICSA,
.regmap_name = "atmel,matrix",
.get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config,
@ -412,6 +419,7 @@ static const struct atmel_ebi_caps at91sam9rl_ebi_caps = {
static const struct atmel_ebi_caps at91sam9g45_ebi_caps = {
.available_cs = 0x3f,
.ebi_csa_offs = AT91SAM9G45_MATRIX_EBICSA,
.regmap_name = "atmel,matrix",
.get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config,
@ -420,6 +428,7 @@ static const struct atmel_ebi_caps at91sam9g45_ebi_caps = {
static const struct atmel_ebi_caps at91sam9x5_ebi_caps = {
.available_cs = 0x3f,
.ebi_csa_offs = AT91SAM9X5_MATRIX_EBICSA,
.regmap_name = "atmel,matrix",
.get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config,
@ -432,6 +441,15 @@ static const struct atmel_ebi_caps sama5d3_ebi_caps = {
.apply_config = sama5_ebi_apply_config,
};
static const struct atmel_ebi_caps sam9x60_ebi_caps = {
.available_cs = 0x3f,
.ebi_csa_offs = AT91_SFR_CCFG_EBICSA,
.regmap_name = "microchip,sfr",
.get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config,
};
static const struct of_device_id atmel_ebi_id_table[] = {
{
.compatible = "atmel,at91sam9260-ebi",
@ -465,6 +483,10 @@ static const struct of_device_id atmel_ebi_id_table[] = {
.compatible = "atmel,sama5d3-ebi",
.data = &sama5d3_ebi_caps,
},
{
.compatible = "microchip,sam9x60-ebi",
.data = &sam9x60_ebi_caps,
},
{ /* sentinel */ }
};
@ -543,13 +565,14 @@ static int atmel_ebi_probe(struct platform_device *pdev)
/*
* The sama5d3 does not provide an EBICSA register and thus does need
* to access the matrix registers.
* to access it.
*/
if (ebi->caps->ebi_csa_offs) {
ebi->matrix =
syscon_regmap_lookup_by_phandle(np, "atmel,matrix");
if (IS_ERR(ebi->matrix))
return PTR_ERR(ebi->matrix);
ebi->regmap =
syscon_regmap_lookup_by_phandle(np,
ebi->caps->regmap_name);
if (IS_ERR(ebi->regmap))
return PTR_ERR(ebi->regmap);
}
ret = of_property_read_u32(np, "#address-cells", &val);

20
drivers/mtd/Kconfig
View File

@ -60,22 +60,6 @@ config MTD_CMDLINE_PARTS
If unsure, say 'N'.
config MTD_AFS_PARTS
tristate "ARM Firmware Suite partition parsing"
depends on (ARM || ARM64)
help
The ARM Firmware Suite allows the user to divide flash devices into
multiple 'images'. Each such image has a header containing its name
and offset/size etc.
If you need code which can detect and parse these tables, and
register MTD 'partitions' corresponding to each image detected,
enable this option.
You will still need the parsing functions to be called by the driver
for your particular device. It won't happen automatically. The
'physmap' map driver (CONFIG_MTD_PHYSMAP) does this, for example.
config MTD_OF_PARTS
tristate "OpenFirmware partitioning information support"
default y
@ -94,6 +78,7 @@ config MTD_BCM63XX_PARTS
tristate "BCM63XX CFE partitioning support"
depends on BCM63XX || BMIPS_GENERIC || COMPILE_TEST
select CRC32
select MTD_PARSER_IMAGETAG
help
This provides partition parsing for BCM63xx devices with CFE
bootloaders.
@ -230,12 +215,11 @@ config SSFDC
This enables read only access to SmartMedia formatted NAND
flash. You can mount it with FAT file system.
config SM_FTL
tristate "SmartMedia/xD new translation layer"
depends on BLOCK
select MTD_BLKDEVS
select MTD_NAND_ECC
select MTD_NAND_ECC_SW_HAMMING
help
This enables EXPERIMENTAL R/W support for SmartMedia/xD
FTL (Flash translation layer).

1
drivers/mtd/Makefile
View File

@ -9,7 +9,6 @@ mtd-y := mtdcore.o mtdsuper.o mtdconcat.o mtdpart.o mtdchar.o
obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o
obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o
obj-$(CONFIG_MTD_AFS_PARTS) += afs.o
obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o
obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o
obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o

266
drivers/mtd/afs.c
View File

@ -1,266 +0,0 @@
/*======================================================================
drivers/mtd/afs.c: ARM Flash Layout/Partitioning
Copyright © 2000 ARM Limited
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
This is access code for flashes using ARM's flash partitioning
standards.
======================================================================*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/partitions.h>
#define AFSV1_FOOTER_MAGIC 0xA0FFFF9F
struct footer_v1 {
u32 image_info_base; /* Address of first word of ImageFooter */
u32 image_start; /* Start of area reserved by this footer */
u32 signature; /* 'Magic' number proves it's a footer */
u32 type; /* Area type: ARM Image, SIB, customer */
u32 checksum; /* Just this structure */
};
struct image_info_v1 {
u32 bootFlags; /* Boot flags, compression etc. */
u32 imageNumber; /* Unique number, selects for boot etc. */
u32 loadAddress; /* Address program should be loaded to */
u32 length; /* Actual size of image */
u32 address; /* Image is executed from here */
char name[16]; /* Null terminated */
u32 headerBase; /* Flash Address of any stripped header */
u32 header_length; /* Length of header in memory */
u32 headerType; /* AIF, RLF, s-record etc. */
u32 checksum; /* Image checksum (inc. this struct) */
};
static u32 word_sum(void *words, int num)
{
u32 *p = words;
u32 sum = 0;
while (num--)
sum += *p++;
return sum;
}
static int
afs_read_footer_v1(struct mtd_info *mtd, u_int *img_start, u_int *iis_start,
u_int off, u_int mask)
{
struct footer_v1 fs;
u_int ptr = off + mtd->erasesize - sizeof(fs);
size_t sz;
int ret;
ret = mtd_read(mtd, ptr, sizeof(fs), &sz, (u_char *)&fs);
if (ret >= 0 && sz != sizeof(fs))
ret = -EINVAL;
if (ret < 0) {
printk(KERN_ERR "AFS: mtd read failed at 0x%x: %d\n",
ptr, ret);
return ret;
}
/*
* Does it contain the magic number?
*/
if (fs.signature != AFSV1_FOOTER_MAGIC)
return 0;
/*
* Check the checksum.
*/
if (word_sum(&fs, sizeof(fs) / sizeof(u32)) != 0xffffffff)
return 0;
/*
* Don't touch the SIB.
*/
if (fs.type == 2)
return 0;
*iis_start = fs.image_info_base & mask;
*img_start = fs.image_start & mask;
/*
* Check the image info base. This can not
* be located after the footer structure.
*/
if (*iis_start >= ptr)
return 0;
/*
* Check the start of this image. The image
* data can not be located after this block.
*/
if (*img_start > off)
return 0;
return 1;
}
static int
afs_read_iis_v1(struct mtd_info *mtd, struct image_info_v1 *iis, u_int ptr)
{
size_t sz;
int ret, i;
memset(iis, 0, sizeof(*iis));
ret = mtd_read(mtd, ptr, sizeof(*iis), &sz, (u_char *)iis);
if (ret < 0)
goto failed;
if (sz != sizeof(*iis)) {
ret = -EINVAL;
goto failed;
}
ret = 0;
/*
* Validate the name - it must be NUL terminated.
*/
for (i = 0; i < sizeof(iis->name); i++)
if (iis->name[i] == '\0')
break;
if (i < sizeof(iis->name))
ret = 1;
return ret;
failed:
printk(KERN_ERR "AFS: mtd read failed at 0x%x: %d\n",
ptr, ret);
return ret;
}
static int parse_afs_partitions(struct mtd_info *mtd,
const struct mtd_partition **pparts,
struct mtd_part_parser_data *data)
{
struct mtd_partition *parts;
u_int mask, off, idx, sz;
int ret = 0;
char *str;
/*
* This is the address mask; we use this to mask off out of
* range address bits.
*/
mask = mtd->size - 1;
/*
* First, calculate the size of the array we need for the
* partition information. We include in this the size of
* the strings.
*/
for (idx = off = sz = 0; off < mtd->size; off += mtd->erasesize) {
struct image_info_v1 iis;
u_int iis_ptr, img_ptr;
ret = afs_read_footer_v1(mtd, &img_ptr, &iis_ptr, off, mask);
if (ret < 0)
break;
if (ret) {
ret = afs_read_iis_v1(mtd, &iis, iis_ptr);
if (ret < 0)
break;
if (ret == 0)
continue;
sz += sizeof(struct mtd_partition);
sz += strlen(iis.name) + 1;
idx += 1;
}
}
if (!sz)
return ret;
parts = kzalloc(sz, GFP_KERNEL);
if (!parts)
return -ENOMEM;
str = (char *)(parts + idx);
/*
* Identify the partitions
*/
for (idx = off = 0; off < mtd->size; off += mtd->erasesize) {
struct image_info_v1 iis;
u_int iis_ptr, img_ptr;
/* Read the footer. */
ret = afs_read_footer_v1(mtd, &img_ptr, &iis_ptr, off, mask);
if (ret < 0)
break;
if (ret == 0)
continue;
/* Read the image info block */
ret = afs_read_iis_v1(mtd, &iis, iis_ptr);
if (ret < 0)
break;
if (ret == 0)
continue;
strcpy(str, iis.name);
parts[idx].name = str;
parts[idx].size = (iis.length + mtd->erasesize - 1) & ~(mtd->erasesize - 1);
parts[idx].offset = img_ptr;
parts[idx].mask_flags = 0;
printk(" mtd%d: at 0x%08x, %5lluKiB, %8u, %s\n",
idx, img_ptr, parts[idx].size / 1024,
iis.imageNumber, str);
idx += 1;
str = str + strlen(iis.name) + 1;
}
if (!idx) {
kfree(parts);
parts = NULL;
}
*pparts = parts;
return idx ? idx : ret;
}
static struct mtd_part_parser afs_parser = {
.parse_fn = parse_afs_partitions,
.name = "afs",
};
module_mtd_part_parser(afs_parser);
MODULE_AUTHOR("ARM Ltd");
MODULE_DESCRIPTION("ARM Firmware Suite partition parser");
MODULE_LICENSE("GPL");

163
drivers/mtd/bcm63xxpart.c
View File

@ -34,6 +34,7 @@
#include <linux/vmalloc.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/of.h>
#define BCM963XX_CFE_BLOCK_SIZE SZ_64K /* always at least 64KiB */
@ -93,51 +94,19 @@ static int bcm63xx_read_nvram(struct mtd_info *master,
return 0;
}
static int bcm63xx_read_image_tag(struct mtd_info *master, const char *name,
loff_t tag_offset, struct bcm_tag *buf)
{
int ret;
size_t retlen;
u32 computed_crc;
ret = mtd_read(master, tag_offset, sizeof(*buf), &retlen, (void *)buf);
if (ret)
return ret;
if (retlen != sizeof(*buf))
return -EIO;
computed_crc = crc32_le(IMAGETAG_CRC_START, (u8 *)buf,
offsetof(struct bcm_tag, header_crc));
if (computed_crc == buf->header_crc) {
STR_NULL_TERMINATE(buf->board_id);
STR_NULL_TERMINATE(buf->tag_version);
pr_info("%s: CFE image tag found at 0x%llx with version %s, board type %s\n",
name, tag_offset, buf->tag_version, buf->board_id);
return 0;
}
pr_warn("%s: CFE image tag at 0x%llx CRC invalid (expected %08x, actual %08x)\n",
name, tag_offset, buf->header_crc, computed_crc);
return 1;
}
static const char * const bcm63xx_cfe_part_types[] = {
"bcm963xx-imagetag",
NULL,
};
static int bcm63xx_parse_cfe_nor_partitions(struct mtd_info *master,
const struct mtd_partition **pparts, struct bcm963xx_nvram *nvram)
{
/* CFE, NVRAM and global Linux are always present */
int nrparts = 3, curpart = 0;
struct bcm_tag *buf = NULL;
struct mtd_partition *parts;
int ret;
unsigned int rootfsaddr, kerneladdr, spareaddr;
unsigned int rootfslen, kernellen, sparelen, totallen;
int nrparts = 3, curpart = 0;
unsigned int cfelen, nvramlen;
unsigned int cfe_erasesize;
int i;
bool rootfs_first = false;
cfe_erasesize = max_t(uint32_t, master->erasesize,
BCM963XX_CFE_BLOCK_SIZE);
@ -146,83 +115,9 @@ static int bcm63xx_parse_cfe_nor_partitions(struct mtd_info *master,
nvramlen = nvram->psi_size * SZ_1K;
nvramlen = roundup(nvramlen, cfe_erasesize);
buf = vmalloc(sizeof(struct bcm_tag));
if (!buf)
return -ENOMEM;
/* Get the tag */
ret = bcm63xx_read_image_tag(master, "rootfs", cfelen, buf);
if (!ret) {
STR_NULL_TERMINATE(buf->flash_image_start);
if (kstrtouint(buf->flash_image_start, 10, &rootfsaddr) ||
rootfsaddr < BCM963XX_EXTENDED_SIZE) {
pr_err("invalid rootfs address: %*ph\n",
(int)sizeof(buf->flash_image_start),
buf->flash_image_start);
goto invalid_tag;
}
STR_NULL_TERMINATE(buf->kernel_address);
if (kstrtouint(buf->kernel_address, 10, &kerneladdr) ||
kerneladdr < BCM963XX_EXTENDED_SIZE) {
pr_err("invalid kernel address: %*ph\n",
(int)sizeof(buf->kernel_address),
buf->kernel_address);
goto invalid_tag;
}
STR_NULL_TERMINATE(buf->kernel_length);
if (kstrtouint(buf->kernel_length, 10, &kernellen)) {
pr_err("invalid kernel length: %*ph\n",
(int)sizeof(buf->kernel_length),
buf->kernel_length);
goto invalid_tag;
}
STR_NULL_TERMINATE(buf->total_length);
if (kstrtouint(buf->total_length, 10, &totallen)) {
pr_err("invalid total length: %*ph\n",
(int)sizeof(buf->total_length),
buf->total_length);
goto invalid_tag;
}
kerneladdr = kerneladdr - BCM963XX_EXTENDED_SIZE;
rootfsaddr = rootfsaddr - BCM963XX_EXTENDED_SIZE;
spareaddr = roundup(totallen, master->erasesize) + cfelen;
if (rootfsaddr < kerneladdr) {
/* default Broadcom layout */
rootfslen = kerneladdr - rootfsaddr;
rootfs_first = true;
} else {
/* OpenWrt layout */
rootfsaddr = kerneladdr + kernellen;
rootfslen = spareaddr - rootfsaddr;
}
} else if (ret > 0) {
invalid_tag:
kernellen = 0;
rootfslen = 0;
rootfsaddr = 0;
spareaddr = cfelen;
} else {
goto out;
}
sparelen = master->size - spareaddr - nvramlen;
/* Determine number of partitions */
if (rootfslen > 0)
nrparts++;
if (kernellen > 0)
nrparts++;
parts = kzalloc(sizeof(*parts) * nrparts + 10 * nrparts, GFP_KERNEL);
if (!parts) {
ret = -ENOMEM;
goto out;
}
if (!parts)
return -ENOMEM;
/* Start building partition list */
parts[curpart].name = "CFE";
@ -230,30 +125,6 @@ invalid_tag:
parts[curpart].size = cfelen;
curpart++;
if (kernellen > 0) {
int kernelpart = curpart;
if (rootfslen > 0 && rootfs_first)
kernelpart++;
parts[kernelpart].name = "kernel";
parts[kernelpart].offset = kerneladdr;
parts[kernelpart].size = kernellen;
curpart++;
}
if (rootfslen > 0) {
int rootfspart = curpart;
if (kernellen > 0 && rootfs_first)
rootfspart--;
parts[rootfspart].name = "rootfs";
parts[rootfspart].offset = rootfsaddr;
parts[rootfspart].size = rootfslen;
if (sparelen > 0 && !rootfs_first)
parts[rootfspart].size += sparelen;
curpart++;
}
parts[curpart].name = "nvram";
parts[curpart].offset = master->size - nvramlen;
parts[curpart].size = nvramlen;
@ -263,22 +134,13 @@ invalid_tag:
parts[curpart].name = "linux";
parts[curpart].offset = cfelen;
parts[curpart].size = master->size - cfelen - nvramlen;
parts[curpart].types = bcm63xx_cfe_part_types;
for (i = 0; i < nrparts; i++)
pr_info("Partition %d is %s offset %llx and length %llx\n", i,
parts[i].name, parts[i].offset, parts[i].size);
pr_info("Spare partition is offset %x and length %x\n", spareaddr,
sparelen);
*pparts = parts;
ret = 0;
out:
vfree(buf);
if (ret)
return ret;
return nrparts;
}
@ -311,9 +173,16 @@ out:
return ret;
};
static const struct of_device_id parse_bcm63xx_cfe_match_table[] = {
{ .compatible = "brcm,bcm963xx-cfe-nor-partitions" },
{},
};
MODULE_DEVICE_TABLE(of, parse_bcm63xx_cfe_match_table);
static struct mtd_part_parser bcm63xx_cfe_parser = {
.parse_fn = bcm63xx_parse_cfe_partitions,
.name = "bcm63xxpart",
.of_match_table = parse_bcm63xx_cfe_match_table,
};
module_mtd_part_parser(bcm63xx_cfe_parser);

2
drivers/mtd/chips/cfi_cmdset_0002.c
View File

@ -869,6 +869,7 @@ static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr
/* Only if there's no operation suspended... */
if (mode == FL_READY && chip->oldstate == FL_READY)
return 0;
/* fall through */
default:
sleep:
@ -2751,6 +2752,7 @@ static void cfi_amdstd_sync (struct mtd_info *mtd)
* as the whole point is that nobody can do anything
* with the chip now anyway.
*/
/* fall through */
case FL_SYNCING:
mutex_unlock(&chip->mutex);
break;

6
drivers/mtd/chips/cfi_util.c
View File

@ -109,10 +109,13 @@ map_word cfi_build_cmd(u_long cmd, struct map_info *map, struct cfi_private *cfi
case 8:
onecmd |= (onecmd << (chip_mode * 32));
#endif
/* fall through */
case 4:
onecmd |= (onecmd << (chip_mode * 16));
/* fall through */
case 2:
onecmd |= (onecmd << (chip_mode * 8));
/* fall through */
case 1:
;
}
@ -162,10 +165,13 @@ unsigned long cfi_merge_status(map_word val, struct map_info *map,
case 8:
res |= (onestat >> (chip_mode * 32));
#endif
/* fall through */
case 4:
res |= (onestat >> (chip_mode * 16));
/* fall through */
case 2:
res |= (onestat >> (chip_mode * 8));
/* fall through */
case 1:
;
}

2
drivers/mtd/devices/Kconfig
View File

@ -207,7 +207,7 @@ comment "Disk-On-Chip Device Drivers"
config MTD_DOCG3
tristate "M-Systems Disk-On-Chip G3"
select BCH
select BCH_CONST_PARAMS if !MTD_NAND_BCH
select BCH_CONST_PARAMS if !MTD_NAND_ECC_SW_BCH
select BITREVERSE
help
This provides an MTD device driver for the M-Systems DiskOnChip

Some files were not shown because too many files have changed in this diff Show More